Fraunhofer IPMS develops TSN Switch IP Core

Innovative IP designs for reliable data transmission - Fraunhofer IPMS develops TSN Switch IP Core

September 30, 2020 -- Time Sensitive Networking (TSN) is an extension of the IEEE 802.1 standard and aims to create reliable, deterministic and convergent Ethernet networks. The Fraunhofer IPMS now completes its TSN IP Core family with a TSN Switch IP Core and will present the innovation at the TSN/A Conference from October 7-8, 2020.

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Proprietary Ethernet field buses have been the standard for real-time and deterministic data transmission for control and automation purposes for decades. TSN could gradually replace these real-time-capable fieldbus systems and brings together the different types of data traffic with different requirements in one network.

"Not only do the network's data traffic requirements vary, but also the topologies and the devices used in the network," explains Marcus Pietzsch (group leader IP core and ASIC design). To meet the different requirements, Fraunhofer IPMS has developed three different TSN IP cores. The TSN-EP is intended for the implementation of end devices such as sensors or actuators in an Ethernet network. The TSN-SE is intended for switched endpoints and can be used for end devices in daisy-chain topologies. The TSN-SW, the latest development, is suitable for multiport switches with or without integrated endpoint functions.

The platform-independent Time Sensitive Networking IP core designs developed by Fraunhofer IPMS facilitate the integration of TSN in devices to be used in an Ethernet TSN network and are optimized for lowest latencies. The IP cores are silicon proven for ASIC technologies up to 22nm. In addition, they can be implemented in FPGAs from various manufacturers.

The multidisciplinary IP design team of the Fraunhofer IPMS with expertise in domain-specific computer architectures, RTL design and implementation of electronic systems is also available as a competent development partner for application-specific adaptations of the IP cores and their integration into complex network architectures.

Registration and further information can be found here.

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