SANTA CLARA, California –September, 30 2020 – Blue Pearl Software Inc.,today announces that Japan’s Toshiba Information Systems, a leading company in information services, has adopted the Blue Pearl Visual Verification™ Suite to improve the productivity and quality of their FPGA and ASIC development.
“Toshiba Information Systems fully utilizes new technology and combines its abundant experience and technical knowledge to develop unique solutions that leverage both FPGAs and ASICs. As such, we are excited to add the Visual Verification Suite to enhance our design methodology,” said Shinji Miyazawa, Senior Manager at Toshiba Information Systems. “In addition to verifying our RTL as we develop it, we look forward to the faster design iterations and improved efficiency.”
With the Visual Verification Suite, designers verify as they code. The suite features HDL Creator™ smart editor, Analyze™ RTL advanced static and formal linting, an integrated debug environment, enhanced Clock Domain Crossing (CDC) analysis and automated SDC generation. An integrated Management Dashboard is also provided to track progress and deliver signoff statistics for audits and design reviews. The suite is designed to complement and extend the verification capabilities provided by the FPGA and ASIC vendor offerings. As part of this agreement, Toshiba Information Systems will be leveraging the suite’s RTL analysis in both Japan and Vietnamto streamline their development process.
“We are pleased to partner with Toshiba Information Systems to help met their productivity goals,” said Fumiko Suzuki, Blue Pearl’s Vice President of Asia Sales. “They are committed to the challenges associated with the accelerated pace of change in information technology, and Blue Pearl is committed to help accelerate their FPGA and ASIC development process by catching structural and coding style errors earlier in their development process.”
About Blue Pearl Software
Blue Pearl Software, Inc.is a leading provider of DO-254 compatible design automation software for ASIC, FPGA and IP RTL verification. Our customers are RTL managers and developers, in military, aerospace, semiconductor, medical, communications and safety critical design companies. The Visual Verification™ Suite speeds block and project level verification with advanced integrated RTL structural and formal linting, constraint generation and clock domain crossing analysis. Our usability is unmatched in the industry and can help your design team accelerate development and produce high reliability designs.The Visual Verification Suite is designed, tested and supported in the United States of America. To learn more about Blue Pearl visit www.bluepearlsoftware.com.