Bell Labs to license turbo decoder chip for 3G terminals

Bell Labs to license turbo decoder chip for 3G terminals
By John Walko, CommsDesign.com
February 12, 2003 (10:19 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030212S0007

San Francisco — Bell Labs has upped the stakes in the drive towards high data rate chips for third generation (3G) devices, describing at the International Solid State Circuits Conference (ISSCC) here architectural and performance details of what it claims is the world's first turbo decoder chip that supports HSDPA (High Speed Downlink Packet Access), an evolutionary enhancement to UMTS/WCDMA technology.

The turbo decoder processes 3rd Generation Partnership Project (3GPP) compliant data streams, including HSDPA, with up to 16 decoder iterations. The LogMAP core processes two received symbols per clock cycle using a windowed radix-4 architecture, doubling the throughput for a given clock rate over a similar radix-2 architecture.

The decoder was developed by a Bell Labs team in Sydney, Australia. The same group announced last October the industry's first chip that incorporates Bell Labs Layered Space Time (BLAST) MIMO (Multiple Input/ Mult iple Output) technology for mobile communications. The BLAST chip enables terminals to receive data at 19.2 Mbit/s in a 3G mobile network.

The researchers said the very high data rate was achieved by employing a novel implementation of turbo codes. The chip also can be reconfigured for different packet sizes and data rates on the fly, making it compatible with the variable data rates arising from Adaptive Modulation and Coding (AMC) -- a key capacity-enhancing feature of HSDPA.

The designers chose a highly parallel architecture for the turbo decoder chip and employed a compression technique that enables it to operate at a low clock frequency and yet still achieve high data rates. By operating at low clock frequencies, the chip consumes very little power.

In their paper at the ISSCC, the researchers said the device, which will be made in 0.18micron CMOS, operates at a peak clock frequency of 145MHz at 1.8V, and dissipates just 956mW when decoding continuous 10.8Mbit/s HSDPA data streams. Power is reduced using the half iteration Hard Decision Assisted stopping criteria to as low as 189mW for 10.8Mbit/s.

Bell Labs says this dynamic power reduction technique can easily adjust the amount of power the decoder consumes depending upon how and where the chip is being used - for example, offering more power if a user is driving in a car than if he or she is stationary in an office.

Commenting on what Bell Labs suggests is a major breakthrough, Ran Yan, vice president of wireless research at the company said "Bell Labs is developing the high-performance, low-power communications components that are needed to make HSDPA devices a commercial reality.

"Turbo codes enable error correction at speeds close to the theoretical limit predicted by Information Theory. Our turbo decoder chip, therefore, is nearly the fastest possible for mobile systems."