MorethanIP releases a 1000Base-X PCS (Physical Coding Sub-Layer) Core which can be used to develop multiport Gigabit Ethernet PHY devices. The Core implements the requirements of the IEEE802.3 Clause 32 specification, 1000Base-X autonegotiation and a MDIO interface with standard and extended management registers. The 1000Base-X PCS Core optionally implements a Gigabit PMA SERDES when implemented in an Altera GX CPLD or in an Altera Mercury ASSP providing a highly integrated solution.
MorethanIP releases a combined Gigabit Ethernet MAC / PHY in a Single Core solution. The Combined MAC / PHY Core integrate MorethanIP configurable 10/100/1000 Ethernet MAC core and MorethanIP new 1000Base-X PCS Core and can be implemented in Programmable Logic Devices or ASICs. With the the MAC / PHY Core the external PHY device typically implemented together with a MAC Device / Core which simplifies system design and reduces costs. When implemented in an Altera Stratix GX CPLD, the solution provides a 1.25Gbps serial MDI interface which can directly be connected to a backplane or an Optical transceiver. On the client interface, the MAC / PHY Core implements a simple FIFO interface which can be connected to all MorethanIP Telecom interface Cores (e.g. POS-PHY Level3) and to a wide range of Third Party Core.