With the capability to operate in either SPI-3 master or slave mode, its integrated packet FIFO and its ability to support data transfer rates in excess of 6Gbps, this IP core is ideally suited to demanding applications such as Bridge Chips
SHEFFIELD, UK – February 14, 2003 – Jennic, a leading supplier of system-level intellectual property (IP) cores and silicon design services, today announced the launch of an IP core that provides an Optical Internetworking Forum (OIF) System Packet Interface Level 3 (SPI-3) compliant interface solution. The SPI-3 Interface IP core is available to system OEMs and semiconductor vendors for incorporation into ASSPs or as an ASIC/FPGA IP library component.
With the gradual displacement of the original OC-48 (2.5Gbps) interface standards of UTOPIA Level 3, from the ATM Forum and POS-Phy Level 3, from the Saturn group, by the OIF's ubiquitous SPI-3 standard, Jennic has upgraded its original product offering in this area to support a number of new features to address the requirements of this new standard. The earlier standards were intended primarily to provide the interface between devices such as SONET Framers (Phy devices) and Cell/Packet Processing Engines (Link Layer devices). However, with the convergence of ATM cell and packet traffic, and in some cases their co-existence over the same interface, there has been a move towards the unified interface standard released by the OIF.
The SPI-3 Interface IP core from Jennic is unique in that it is probably the only available SPI-3 Interface IP core that can be programmed by the user to operate as either a Phy device or a Link Layer device. "This capability was provided to specifically address the needs of bridging applications where the same interface may be connected to a Phy device in one users application and may be connected to a Link Layer device in another," said Frank Newcombe, Business Development Manager for Optical Networks at Jennic. "Currently the most active area in the line card business is OEMs undertaking cost reduction exercises and incremental product upgrades. As the older, obsolete components are being designed out and replaced by best-inclass semiconductor components sourced from a variety of providers, there has been a growth in the requirement for bridge chips to connect these devices together. The SPI-3 Interface IP core is our second product to specifically address this market, following as it does behind our highly successful SPI-4.2 interface IP core that the we launched in November 2002." In the original intended applications, the bandwidth required over the interface was determined primarily by the data rate of the physical media over which the data was being transferred, which for OC-48 SONET was of the order of 2.4Gbps. However with the permeation of the SPI-3 interface across the line card, where its is now being used as the interconnect between devices such as network processors and traffic managers, there is a requirement to significantly increase the available bandwidth to accommodate the transport of additional data such as control packets and tag fields which have been appended to existing packets. Jennic's solution can support an external interface clock rate up to 200MHz, when implemented in a 0.13um ASIC process, giving a theoretical maximum bandwidth of 6.3Gbps.
Designers of today's leading edge devices have pushed back the responsibility of buffering and ordering the packet data to the interface cores to leave them free to concentrate on the higher layer capabilities in the core of their devices. This requires the interfaces to provide complex FIFO architectures specifically designed to handle a fragmented, packetised data flow. Jennic's SPI-3 solution contains a fully integrated, channelised packet FIFO to achieve this.
The SPI-3 IP core is available as a soft IP core for implementing in 0.18um and 0.13um CMOS technologies and high performance FPGAs. A number of options are available to provide additional functionality not normally required by the majority of users. Jennic also provides design services to optimise the IP core to customers specific requirements, such as the addition of proprietary features etc. and to provide ongoing technical sales and marketing support to the end-customer market.
Jennic is a leading provider of System Level Digital and Mixed Signal Intellectual Property and silicon design services to the broadband communications market. Jennic combines its systems expertise, advanced Intellectual Property portfolio and skills in digital, software, mixed signal and SoC design to deliver performance, cost and time-to-market advantages to its system OEM and semiconductor customers. Jennic's Intellectual Property portfolio includes intelligent physical layer framers and high speed interfaces for wide and metropolitan area networks, ATM SAR engines for broadband access networks and mixed signal systems, based on a library of mixed signal modules.
Founded in 1996 Jennic has its headquarters in Sheffield, England.