Esperanto Technologies to Reveal Chip with 1000+ Cores at RISC-V Summit
Art Swift, CEO of Esperanto Technologies, will present chip that accelerates Machine Learning based on RISC-V ISA
MOUNTAIN VIEW, Calif., Dec. 1, 2020 – Esperanto Technologies™, developer of high-performance, energy-efficient computing solutions based on RISC-V for Artificial Intelligence (AI), Machine Learning (ML) and Deep Learning (DL) applications, will participate in the RISC-V Summit, December 8-10, 2020. Art Swift, CEO of Esperanto, will deliver the presentation: Esperanto Accelerates Machine Learning with 1000+ Low-Power RISC-V Cores on a Single Chip on Tuesday, December 8.
Ad |
RISC-V-based SoC template Low-power 32-bit RISC-V processor E31 Balanced performance and efficiency RISC V core |
- What: RISC-V Summit.
- Where: Virtual event, online.
- When: December 8, 2020.
- Agenda: View the agenda here.
- Register here
Presentation: Esperanto Accelerates Machine Learning With 1000+ Low-Power RISC-V Cores on a Single Chip
- Esperanto Technologies has developed a ground-breaking accelerator chip for large-scale machine learning applications employing over 1000 RISC-V cores.
- In this talk, Esperanto provides an overview of the company’s new ET-SoC-1 chip, which features two kinds of general-purpose 64-bit RISC-V cores. The ET-Maxion, previewed at the RISC-V Summit in 2018, is a superscalar out-of-order core delivering high performance for modern operating systems and applications. The complementary ET-Minion core designed by Esperanto is a leaner, energy efficient, in-order multithreaded core with a vector/tensor accelerator unit at the heart of the massively parallel compute array.
- The chip’s performance and efficiency is derived from a combination of factors, including the simplicity of the RISC-V instruction set, wide vector/tensor units on every ET-Minion core, a uniquely optimized memory hierarchy, state of the art process technology, and custom pipeline architecture and low-voltage circuits which enables more energy-efficient operation. The result is that Esperanto will deliver better performance per watt than legacy CPU and GPU solutions, as well as competing fixed-function designs without compromising generally purpose flexibility.
About Esperanto Technologies
Esperanto Technologies develops high-performance, energy-efficient computing solutions for Artificial Intelligence / Machine Learning based on the open standard RISC-V instruction set architecture. Esperanto is headquartered in Mountain View, California with engineering sites in Portland, Oregon and Austin, Texas in the United States and multiple sites in Europe. Esperanto has brought together a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications such as AI and Machine Learning. For more information, please visit https://www.esperanto.ai/
About the RISC-V Summit
The third annual RISC-V Summit will highlight the continued rapid expansion of the RISC-V ecosystem, presenting both commercial offerings and exciting open-source developments. Newcomers to RISC-V, as well as the seasoned developers who are interested in broadening their toolsets, are invited to choose from the broad range of tutorials. The comprehensive 100% virtual event will feature keynotes from industry pioneers as well as thought-provoking panel discussions. Network with thought-leaders, technology companies, and researchers spearheading the adoption of this evolutionary change in the silicon market.
|
Related News
- Esperanto Technologies Plans Energy-Efficient Chips for Artificial Intelligence and Machine Learning, based on the open RISC-V standard
- CAST Enhances RISC-V Processor Line for Low-Power and Functional Safety Applications
- Andes Technology Unveils the AndesCore™ D23, a Feature-Rich, Low-Power and Highly-Secured Entry-Level RISC-V Processor
- Microchip Adds Second Development Tool Offering for Designers Using Its Low-Power PolarFire RISC-V SoC FPGA for Embedded Vision Applications at the Edge
- Imec combines advanced machine learning algorithms and innovations in chip design to achieve cm accuracy and low-power ultra wideband localization
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |