Automated formal solution detects bugs not found by simulation yielding high-quality of results and fast verification signoff
MUNICH, GERMANY – December 7, 2020 – OneSpin Solutions, provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits, announced that its 360 Design Verification (DV) solutions contributed to the speedy, successful, and bug-free delivery of the OpenHW CV32E40P RISC-V core. The OpenHW Verification Task Group recognizing that simulation would not be enough collaborated with OneSpin to develop a verification plan that included formal methods to verify the family of CORE-V open-source RISC-V cores. These processors are intended to be integrated into high-volume, commercial chip projects that will require strict integrity criteria be met with respect to functional correctness, safety, trust and security.
“Working within the OpenHW Group ecosystem to verify the CORE-V family of RISC-V processors is an opportunity to demonstrate the power of our technology,” said Raik Brinkmann, President and CEO of OneSpin. “As these cores get released into the community, users can have confidence that they will be functionally correct, safe, trusted and secure. Of course, designs integrating any IP should still go through rigorous verification but using these exhaustively verified cores will help to reduce that overall effort.”
RISC-V Opportunities and Verification Challenges
RISC-V offers the design community customization and flexibility but creates new challenges beyond the traditional SoC design verification flow. Processor verification is a new requirement that adopters of RISC-V will need to undertake. However, processors cores are difficult to verify. Complex microarchitectures for achieving power, performance, and area targets combined with a vast number of instruction combinations, cache, interrupts, exceptions, and a myriad of custom extensions, all need to be fully verified. Further complicating verification is ensuring that the core is correct with respect to the instruction set architecture (ISA) as well as making sure that the RTL matches the ISA.
The traditional simulation approach requires months of testbench set up, weeks of simulation runtime, and days of debugging a single problem. Even after simulation is implemented, critical corner case bugs can be missed, and designs are left with an incomplete function coverage. Simulation is also unable to detect the absence of hidden instructions. Any user optimization or addition of custom instructions requires a complete re-verification.
OneSpin Work on CORE-V
“OneSpin’s unique technology was an ideal contribution to the OpenHW Verification Task Group helping to identify bugs that simulation alone would have missed,” commented Rick O’Connor, President and CEO of OpenHW Group. “Their solution allowed the task group to achieve the coverage necessary to reach the Functional RTL Freeze signoff goals both in terms of speed and quality.”
OneSpin’s solutions augment the SystemVerilog / UVM based CORE-V Verification Test Bench simulation efforts to produce a robust verification environment to overcome RISC-V verification challenges resulting in zero bug escapes. Once the testbench was implemented, runtime was completed in a matter of days and debugging was finished in just minutes. Exhaustive and complete verification was achieved in a very short period of time. The use of the OneSpin Processor Integrity solution led to the detection of many critical bugs including eight related to regular and exception instructions as well as other aspects of the privileged specification. Simulation alone would have taken weeks and missed these important bugs.
Integrators of CORE-V may access a packaged processor integrity verification solution to verify custom instructions and code optimizations.
Silicon Labs, an integral member of the OpenHW Group helping to lead the verification task group, witnessed first-hand OneSpin’s involvement in the verification effort. “The CV32E40P core, is the first open-source core for high-volume chips verified with the state-of-the-art process required for high-integrity, commercial SoCs. OneSpin is a key contributor. The OneSpin RISC-V integrity formal verification solution has systematically detected corner-case bugs in the exception logic and pipeline. These issues would only be triggered under rare conditions in the instruction sequence, memory stalls, and Control and Status Register programming. Constrained-random simulation tests to find these issues would require large investments in development and simulation time,” stated Steve Richmond, verification manager at Silicon Labs and co-chair of the OpenHW Verification Task Group.
“The pinpointing of the issues' root cause was impressive and a massive time-saver in debug time. The solution also showed almost zero noise in detecting real RTL bugs, as opposed to other approaches where the issues reported often lead to fixes in the verification environment,” added Arjan Bink, principal architect at Silicon Labs and chair of the OpenHW Cores Task Group.
Customizing and Integrating the CV32E40P Core
Although the OpenHW CV32E40P core is fully verified, there are still some verification challenges when integrating the core or if customization of the core is done. Formal verification of the core should be done if any tailored updates to the core’s functionality are made. This step will ensure that the changes do not introduce new bugs that adversely affect how the core operates. When the core is integrated into the design, verification of the complete design should be done to assure the integrity of the design.
To learn more about how OneSpin collaborated within the OpenHW Group ecosystem to verify the CORE-V CV32E40P processor, be sure to visit the OpenHW Pavilion at the RISC-V Virtual Summit, December 8-10, 2020. Sign up to attend the conference session conducted by OpenHW, Silicon Labs, and OneSpin titled, “CORE-V-VERIF, an Industrial-Grade Verification Platform for RISC-V cores.”
About OpenHW and Core-V
The charter of the OpenHW Group is to serve developers of processor cores and hardware and software engineers who design SoCs with greater awareness, understanding and availability of open-source processor implementations for use in high volume production. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices. The cores task group within the organization has the mandate to develop feature and functionality roadmap and the open-source IP for the cores within the OpenHW Group such as the CORE-V Family of open-source RISC-V processors.
The Organization’s Verification Task Group has the mandate to develop best-in-class verification test bench environments for the cores and IP blocks designed within the OpenHW Group. Originally known as the PULP RI5CY core, the CORE-V CV32E40P is a 32bit, 4-stage core that implements, RV32IMFCXpulp, has an optional 32-bit FPU supporting the F extension and instruction set extensions for DSP operations, including hardware loops, SIMD extensions, bit manipulation and post-increment instructions.
About OneSpin Solutions
OneSpin Solutions is a leading provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits. These solutions are based on OneSpin's widely used formal verification technology and assure the integrity of SoCs, ASICs and FPGAs. Headquartered in Munich, Germany, OneSpin partners with leaders worldwide in automotive and industrial applications; defense; avionics; artificial intelligence and machine learning; consumer electronics; and communications. Its advanced solutions are well-suited for developing heterogeneous computing platforms, using programmable logic, and designing and integrating processor cores, such as RISC-V. OneSpin's customer-oriented commitment is fundamental to its growth and success. OneSpin: Assuring IC Integrity. Visit www.OneSpin.com to learn more.