New PureSpec™ Product Offers Pre-silicon Compliance and Interoperability Verification– Provides Customers with Faster Time-to-Market
INTEL DEVELOPER FORUM, SAN JOSE, Calif., Feb. 18, 2003--At the Intel Developers Conference today, Denali Software, Inc., the leading provider of semiconductor intellectual property (SIP) and electronic design automation (EDA) tools for chip interface design and verification, introduced its new product, PureSpec™, which provides chip designers with a complete solution for modeling and verifying pre-silicon compliance and interoperability for PCI Express™ designs.
As the adoption of the PCI Express standard accelerates, chip developers now face the task of verifying their designs for compliance with the PCI Express specifications, and other PCI Express designs. Correct implementation of the PCI Express standard is necessary for multiple chips to communicate in the final system--any design errors or misinterpretations of the protocol specification could ultimately mean failure for the entire system or end product.
Teams designing large chips commonly spend more than half of their resources on functional verification, simulating their designs with software to detect errors before implementing their design in silicon. The cost and time-to-market impact of errors caught in the lab after the design has been implemented in silicon can be orders of magnitude greater than those caught during functional verification. Denali's PureSpec product addresses these issues and provides designers with a complete pre-silicon verification solution for PCI Express designs, including: modeling, bus traffic generation, compliance checking, and interoperability analysis.
"The PCI-SIG appreciates Denali's support of the PCI Express specification. Compliance and interoperability verification are key to developing quality products based on PCI Express architecture," said Tony Pierce, PCI-SIG Chairman. "We welcome the efforts of our active members working to enable PCI Express architecture."
"With the completion of the PCI Express specifications in July 2002, the industry turned its attention to delivery of PCI Express solutions," said Jim Pappas, director of initiative marketing for Intel's Enterprise Platform Group. "Modeling and simulation of designs, especially when developing to a new specification, minimize design time and accelerate time to market. We're pleased to see Denali's announcement of availability of verification IP to spur the rapid delivery of PCI Express enabled solutions and welcome their participation at the first PCI Express community at IDF."
"We are seeing a tremendous amount of interest in PCI Express design verification from our customer base," said Mark Gogolewski, chief technology officer, Denali. "Denali has long been the leader in providing the ASIC design community with advanced verification solutions for complex memory interfaces. Our customers are now asking us to provide the same robust verification IP for PCI Express interfaces. PureSpec provides a powerful solution for verifying compliance with the PCI Express specification, and is the only verification IP to address post-silicon interoperability with other PCI Express devices. We are providing the optimal solution for reducing risk in PCI Express designs."
"With PureSpec, we are delivering a solution that works for the entire PCI Express design community," said David Lin, vice president product marketing, Denali. "Our products are not limited to any one tool or verification language; all our products are designed from the ground up to support all EDA tools and verification languages equally. Having a unified representation of the verification IP also enables us to ensure unparalleled quality and performance for our customers."
The PureSpec product is built on the proven product architecture of Denali's MMAV product, which has been used to verify complex memory interfaces for thousands of successful designs, and is integrated to all popular EDA tools and verification languages. Within PureSpec, all protocol layers (physical, data link, transaction) of the PCI Express specification are completely modeled and can be coordinated simultaneously or used separately. PureSpec models all devices in the PCI Express topology, including the root complex, switch, endpoint, and PCI Express to PCI bridge. A generic device conforming to the specification can also be modeled. Composite configurations by port, function, or virtual channel are also supported. PureSpec also helps drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to PCI Express specifications. Proven product platform, dedicated customer support, and unmatched EDA modeling and verification expertise make PureSpec the best-in-class verification IP solution for PCI Express designs. The PureSpec product is available now for customer evaluation at:
About PCI Express Technology
PCI Express Architecture is a state-of-the-art serial interconnect technology from the PCI-SIG that delivers performance headroom and advanced features for expected processor and memory subsystem improvements over the next decade. PCI Express Architecture retains the PCI usage model and software interfaces to facilitate a smooth development migration from existing PCI based designs. The technology is suitable for multiple market segments in the computing and communications industries, and supports chip-to-chip, board-to-board and adapter solutions at an equivalent or lower cost structure than existing PCI designs.
Denali Software Inc. is the world's leading provider of EDA tools and Semiconductor Intellectual Property (SIP) solutions for chip interface design, integration, and verification. PureSpec is the most robust interface verification solution for bus protocol interfaces. Denali's Databahn product provides designers with the highest quality solution for producing memory controller cores for all of the new and emerging DRAM memory technologies. Denali's MMAV product is the de facto industry standard for modeling and simulating memory during all phases of design and verification. Memory selection, memory controller configuration, and memory system performance analysis are supported through Denali's online infrastructure at eMemory.com. More than 400 companies worldwide use Denali's tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. For more information, please visit Denali at www.denali.com or contact Denali directly at: 650/461-7200, or email: firstname.lastname@example.org
The Denali logo, Databahn, eMemory, MMAV, and PureSpec are trademarks of Denali Software, Inc.
PCI Express is a trademark of PCI-SIG. All other trademarks are the property of their respective owners.