Genesys Logic's New GigaCourier Family Delivers Full Coverage from Discrete PHY and Silicon Intellectual Property to PCI Express Bridge Chip for Server, Storage and Networking Applications
INTEL DEVELOPER FORUM, SAN JOSE, Calif., Feb. 18, 2003 -- Genesys Logic, Inc. (GLI) and its US subsidiary, Genesys Logic America, Inc. (GLA), today introduced GigaCourier, a family of products designed to the industry standard PCI Express specification. GigaCourier will allow Genesys Logic customers to leverage the 4x improvement in data transfer rate provided by PCI Express technology over the conventional PCI bus. GigaCourier delivers discrete ASSP solutions, and Genesys Logic's new PCI Express SIP (Silicon Intellectual Property) transceiver and endpoint controller cores can be fully integrated with either ASIC or FPGA, providing customers with flexible solutions in server, storage and networking, as well as PC applications.
The three main GigaCourier products include GigaCourier/PHY, GigaCourier/FPGA and GigaCourier/SFO. GigaCourier/FPGA includes data link and transaction layers to PCI/PCI-X, is available in FPGA or hard macro-cell SIP versions. GigaCourier/SFO is a PCI Express Bridge chip to PCI and PCI-X, covering PHY, data link, and transaction to PCI/PCI-X.
GigaCourier/PHY, Genesys Logic's PCI Express PHY Interface (PPI), is a complete mixed-signal intellectual property (IP) solution for the emerging PCI Express market. With a serial data rate of 2.5Gb/s/dir/lane, GigaCourier/PHY handles low level PCI Express protocol and signaling with features such as data sterilization and deserialization (SerDes); 8b/10b encoding; analog buffers; elastic buffers; and receiver detection. The chip's primary task is to shift the clock domain of the data from the PCI Express rate, making it compatible with the general logic in the ASIC. Even though the PPI PHY is a single-lane implementation, its flexible architecture allows easy adaptation for multiple-lane applications to achieve a much higher bandwidth.
GigaCourier/PHY meets all the specifications defined in Intel's PHY Interface for PCI Express Architecture (PIPE). Genesys Logic's new PPI includes all the physical and logical design needed for easy inclusion in a System-On-a-Chip (SOC) design, and it can be manufactured either in designated or client-specified foundries. The GigaCourier/PHY will be available in ASSP or hard macro-cell SIP, and the initial PHY solution is offered in 0.18ìm, with other process technologies soon to be available.
"We are pleased Genesys Logic has been able to participate in the Intel Developer Network for PCI Express Technology in order to work with other industry leaders to deliver PCI Express solutions," said David Cho, President of Genesys Logic America and Business Development. "As a key innovator in the Intel Developer Network, Genesys Logic is committed to supporting the next generation of I/O architecture that will enable our customers to reach the market more quickly with lower cost and superior quality products."
"Genesys Logic is in a unique position to lead the way in the development of PCI Express cores," said Forster Shih, CEO and President of Genesys Logic. "Our high-speed USB 2.0 cores are already proven in both silicon and SIP, having undergone full compliance testing. As part of our PCI Express roadmap, we will continue to lead the development of standards-compliant cores that provide our customers with significant time-to-market and economic advantages."