Advanced DDR Memory Interface PHY's and Controllers IP Cores available in advanced process nodes including TSMC 7FFC

1^st Feb 2021 – T2M-^IP The global independent semiconductor IP Cores & Technology provider, is pleased to announce the immediate availability of advanced DDR memory subsystem IP Cores comprising of Analog PHY’s and Controllers which support a broad range of DDR SDRAM standards.

DDR IP Core offerings consists of high-performance digital controllers and analog PHY’s supporting DDR5, LPDDR5, DDR4, LPDDR4, DDR3, DDR3L, DDR2. The comprehensive range of analog DDR Phy IP Cores are production proven in TSMC 7FFC, TSMC 12FFC, TSMC 28HPC+, UMC 28HPC+, UMC 40LP technologies. These have been used in many of the semiconductor industry’s fastest growing market segments ranging from Consumer, Enterprise and Embedded solutions.

The DDR IP Core is completely verified and silicon proven in all the above Fabs / Nodes. The PHY IP Cores are optimized for high performance, low latency, low area, low power, ease of integration and faster time-to-market. These standards are used for systems that require high-speed, high-performance, and high capacity memory solutions. The IP Cores supports the complete range of DDR4 DRAM speeds from 0Mbps to 3200Mbps, DDR3 DRAM speeds from 666Mbps to 2133Mbps and DDR2 DRAM speeds from 666Mbps to 1066Mbps. The DDR PHY Cores has the following key characteristics and benefits to customers: High performance, Low system cost, Simple to integrate, Easy timing closure, Automatic training, Simple to bring up

The DDR memory Controller IP Core functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL, this supports LPDDR5/LPDDR4 and DDR 5/4/3/3L/2 optimized for low latency. The Controller IP Core is silicon proven and connects to the DDR PHYs via the DFI interface to provide customers a complete memory interface solution with ease of integration and faster time to market. The Controller IP Cores support x8/x16/x32 DRAM data bus configuration. The DDR controller will convert the internal request to DRAM chip protocol for data read/write, it supports Multi-Ranks DRAM configuration. The DDR controller also implements the DRAM refresh, DRAM dynamic power down, DRAM Scramble and DRAM Private Usage functions.

In addition to DDR, T2M^IP’s broad silicon Interface IP Cores portfolio also includes USB, HDMI, MIPI, PCIe, 10/100/1000 Ethernet, Vx1, Serial ATA, programmable SerDes, etc… which are available in leading technologies TSMC, UMC, SMIC, GF, ST and SAMSUNG.

Availability:

These Interface IP Cores are available for immediate licensing stand alone or integrated with the matching Controllers. For more information on licensing options and pricing please drop a request

About T2M:

T2M^IP is the global independent semiconductor technology provider, supplying complex IP Cores, software, KGD and disruptive technologies enabling accelerated development of your storage, servers, networking, communications, TV, STB, Satellite, and PC cards SoCs. For more information, please visit: www.t-2-m.com

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