VLIW on AMBA
![]() |
VLIW on AMBA
By David Larner, Embedded Systems
August 23, 2001 (11:45 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010823S0030
Siroyan is to deploy ARM's open standard Advanced Microcontroller Bus Architecture (AMBA), both in its first synthesisable core (a "soft core") - code-named Rubicon and its first test chip - code-named Spey. The test chip will be manufactured later this year on UMC's 0.15micron process. Siroyan's processor uses a very long instruction word (VLIW) architecture -- code-named Opus. This combines scalable high-performance DSP and RISC functionality in a single core, together with memory management elements.
Related News
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications
- Digital Blocks AMBA Peripherals I3C, I2C, eSPI, xSPI Controller IP Core Families Extend Leadership with enhancements containing feature-rich, system-level integration features.
- Winbond's Successful Interoperability of OctalNAND Flash with Synopsys DesignWare AMBA IP Delivers Complete High-Density NAND Flash Memory Solution
- PLDA Announces XpressLINK-SOC CXL Controller IP with Support for the AMBA CXS Issue B Protocol
- Synopsys DesignWare CXL IP Supports AMBA CXS Protocol Targeting High-Performance Computing SoCs
Breaking News
- PQSecure Partners with Menta SAS to Demonstrate Leakage-Resistant PQC IPs on eFPGA Fabric
- VESA Releases Compliance Test Specification Model for DisplayPort Automotive Extensions Standard
- Imagination Announces E-Series: A New Era of On-Device AI and Graphics
- Kyocera Licenses Quadric's Chimera GPNPU AI Processor IP
- MIPI C-PHY v3.0 Adds New Encoding Option to Support Next Generation of Image Sensor Applications
Most Popular
- Numem Appoints Former Intel Executives to Leadership Team
- MIPI C-PHY v3.0 Adds New Encoding Option to Support Next Generation of Image Sensor Applications
- Agile Analog appoints CEO to drive growth
- Axiomise Featured Gold Sponsor at RISC-V Summit Europe Next Week in Paris
- Cadence Accelerates Physical AI Applications with Tensilica NeuroEdge 130 AI Co-Processor
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |