SAN Mateo, Calif. IBM Corp. hopes to be the first microprocessor maker to deliver a multi-core, multithreaded CPU when it rolls out its Power5 chip next year. The dual-core chip will handle four threads simultaneously in a design that could give server makers a four-fold performance boost over systems using IBM's current Power4 processor.
"We expect this to be very significant especially on applications such as transaction processing that have a high degree of data dependencies. With Power5 it appears to the operating system that there are four CPUs on each chip," said Mark Papermaster, director of microprocessor design for IBM's server division.
Multicore, multithreaded design has become a mantra in server processors.
Intel recently announced it intends to release a dual-core version of its 64-bit Itanium2 microprocessor in 2005, see related story. The company alre ady ships dual-threaded 32-bit Pentium4 and Xeon processors.
For its part, Sun Microsystems plans to roll out a dual-core, single-threaded UltraSparc IV chip this year. Sun has also tipped plans for a new H series family that could run as many as 32 threads based on eight simplified UltraSparc II cores each running four threads.
IBM launched the Power4, the first dual-core server CPU, in 2001. With the Power5, it now hopes to be the first to blend both multi-core and multithreading technologies.
"We were the first to market with two cores on a die, and we wanted to be the first to bring these capabilities to market as well," Papermaster said.
IBM will not detail how well its implementation of mutltithreading will perform, but Papermaster did say he expects an overall four-fold performance improvement of Power5 over Power4 systems.
"We have the chip back and we are in early testing of the processor. It is performing exactly as we hoped," said Papermaster. "It's a very efficient implementation of simultaneous multithreading, so we expect to get high productivity gains," he added.
The Power5 sports a new CPU core with execution units redesigned for multithreading. The chip, currently made using a 130-nm process, will debut at data rates faster than 1.5 GHz.
IBM is not revealing the cache structure for the processor yet. However Papermaster said the Power5 uses a new technique for fast data transfers between regions of main memory. The Power4 uses an external 32 Mbyte level-three cache module.