By Sally Ward-Foxton, EETimes (April 8, 2021)
At the TinyML Summit, early-stage analog AI accelerator startup Areanna presented the first public reveal of its architecture, disclosing some of the features of its 40 TOPS/W SRAM array-based design. The unusual design integrates analog-to-digital and digital-to-analog conversion within the memory array. Since ADCs and DACs typically take up the vast majority of silicon area and power budget for compute-in-memory designs, integrating this functionality within the memory array could be a game changer for analog compute technology.
Areanna is led by former Tektronix analog design engineer Behdad Youssefi alongside another ex-Tek colleague, Patrick Satarzadeh. They remain the company’s only two full-time employees, alongside a couple of part time engineers and several advisors. The company has achieved a test chip with one computing tile based on its architecture up and running.
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