Ventana is designing a range of data center class compute chiplets leveraging the open RISC-V instruction set architecture
CUPERTINO, Calif.-- September 1, 2021 -- Ventana Micro Systems Inc., a company developing high-performance data center class RISC-V processors, today announced that the company has raised $38 million in its Series B funding round. The round was led by Dr. Sehat Sutardja and Weili Dai (founders of Marvell Technology Group) and other prominent semiconductor investors in partnership with Series A investors, which include a notable strategic partner, bringing Ventana’s total funding to $53 million.
Ventana was founded in 2018 by Balaji Baktha and Greg Favor, industry veterans with a proven track record of delivering high-performance processors. Ventana offers data center class high-performance RISC-V CPUs with extensible instruction set capability delivered in the form of multi-core chiplets. The company also offers a customizable SoC chiplet enabling hyperscalers and others to achieve rapid productization while being able to innovate and differentiate. Ventana’s compute chiplets are designed to deliver best-in-class single thread performance optimized for cloud, enterprise data center, 5G, edge compute and automotive applications. Ventana’s unique microarchitectural innovations make its design highly portable across different fabs and process nodes.
“Nearly half of compute spend is moving away from general purpose processors in favor of infrastructure compute and domain specific accelerators,” said Balaji Baktha, Founder and CEO of Ventana. “Ventana is perfectly positioned to capitalize on this trend with our high-performance cores built on the extensible RISC-V architecture, and our chiplet-based rapid productization approach.”
“Ventana has created an innovative RISC-V architecture that addresses the market need for a high-performance, customizable and secure processor solution,” said Eyal Dagan, Executive Vice President of the Common Hardware Group at Cisco Systems.
Ventana’s modular, scalable chiplet-based product strategy enables significant reduction in development time and cost compared to the prevailing IP model. While Ventana’s compute chiplets maximize performance by targeting cutting edge process geometries, customers can implement their unique SoC chiplet silicon in the most optimal process node for the target application. To ensure interoperability, Ventana offers a parallel die-to-die (D2D) solution capable of very low latencies, high bandwidth and lowest power. The D2D solution is compliant with the OCP Open Domain-Specific Architecture (ODSA) physical interface standard.
“Ventana’s high-performance solutions have the potential to reshape silicon design as we know it, making it possible for companies to develop super powerful solutions in record time and without an extensive budget. We believe this approach to be revolutionary in several growth markets including data center, 5G, automotive, enterprise and client computing,” said Dr. Sehat Sutardja.
“As Moore’s Law is slowing, the industry is moving towards chiplet-based designs that optimize cost by using the right process node for each component of the design,” noted Linley Gwennap, principal analyst at The Linley Group. "Ventana’s chiplet strategy accelerates deployment of this emerging approach across a broad range of customers and partners while tapping rising adoption of the open-source RISC-V architecture.”
“Ventana is a great example of how RISC-V is unleashing new design possibilities, including data center implementation which has been traditionally dominated by proprietary approaches,” said Calista Redmond, CEO of RISC-V International. “RISC-V has no licensing costs with complete design flexibility, providing Ventana’s customers with both cost and innovation advantages.”
To learn more about Ventana Micro Systems Inc., please visit: https://www.ventanamicro.com/.
About Ventana Micro Systems Inc.
Headquartered in Cupertino, Ventana Micro Systems Inc. was founded in 2018 to revolutionize the processor market by offering high-performance, extensible and secure compute chiplets based on RISC-V’s open architecture.