Codasip Strengthens Senior Leadership Team
Rupert Baines joins as Chief Marketing Officer
Munich, Germany – September 9, 2021 – Codasip, the leading supplier of customizable RISC-V processor IP and tools, announced today that semiconductor industry veteran Rupert Baines has joined the company as Chief Marketing Officer and member of the management supervisory board.
Mr. Baines was most recently Chief Executive Officer of UltraSoC, a UK-based provider of semiconductor IP and analytics solutions that put intelligent monitoring, cybersecurity, and functional safety capabilities into the core hardware of system-on-chips (SoCs). The company, based in Cambridge, was sold to Siemens in June 2020.
“I am very pleased to welcome Rupert to the Codasip team,” said Dr Ron Black, Executive Chairman of Codasip. “He brings a wealth of experience in RISC-V and semiconductors, which are core to Codasip, and his strategic insight is a key part of our plans.” Dr Karel Masařík, Founder and CEO of Codasip, commented: “We worked very closely with Rupert and the UltraSoC team for many years and were extremely impressed by how he positioned and built the company. We are pleased to welcome him as part of the team as we grow.” Mr. Baines continued: “Codasip has very strong technology and very good customer traction but has not been as well known as it deserves. From marketing perspective, this is a great opportunity and an exciting challenge that I can't wait to meet.”
Prior to his tenure at UltraSoC/Siemens, Mr. Baines held senior executive positions in technology companies such as Real Wireless, Mindspeed Technologies, and Picochip. His broad work experience includes strategic consultancy and fundraising, with several successful start-ups and exits. He is a Fellow of the IET, holds degrees in Electronic Engineering from the University of Hull and an MBA from IESE.
About Codasip
Codasip delivers leading-edge RISC-V processor IP and high-level processor design tools, providing IC designers with all the advantages of the RISC-V open ISA, along with the unique ability to customize the processor IP. As a founding member of RISC-V International and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded and application processors. Formed in 2014 and headquartered in Munich, Germany, Codasip currently has R&D centers in Europe and sales representatives worldwide. For more information about our products and services, visit www.codasip.com. For more information about RISC-V, visit www.riscv.org.
|
Codasip Hot IP
Related News
- Siemens strengthens leadership in industrial software and AI with acquisition of Altair Engineering
- Rupert Baines joins Nanusens board
- Secure-IC strengthens its innovation leadership in embedded cybersecurity with the acquisition of eShard patents portfolio
- SiFive's RISC-V Leadership Strengthens with New Vector Solutions
- Wipro to acquire Eximius Design, strengthens leadership in VLSI and systems design services
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |