Ken Potts joins the Alphacore team as Chief Operating Officer
Tempe, AZ — Sept 15, 2021 -- Alphacore Inc., an industry leader in high-performance analog and RF design, has appointed Ken Potts as its Chief Operating Officer. Potts will guide the company in accelerating its already strong financial growth with commercial products and Intellectual Property (IP) licensing by leveraging a deep portfolio of high-performance and industry leading data-conversion circuits.
“Ken is a semiconductor industry veteran who is uniquely qualified to expand our business,” said Esko Mikkola, chairman and CEO, Alphacore. “I look forward to seeing him execute our mission”
Ken has held numerous executive and operational leadership roles in Semiconductor Products, Semiconductor IP, and Electronic Design Automation. In his tenure with Cadence Design Systems [NASDAQ: CDNS] he led strategy and business intelligence initiatives resulting in a doubling of revenue. Prior to Cadence, Potts led Marketing and Worldwide Sales at Virage Logic [NASDAQ: VIRL, acquired by SNPS], going from losses to profitability, growth, and successful IPO. Prior to Alphacore, Ken was SVP of Product Management at Silicon Technologies Inc. where he drove new product development and market introduction, resulting in dramatic growth in revenue and profit margin.
“I’m delighted to have the opportunity to lead such a great organization. Alphacore is a growing and dynamic organization with excellent technology differentiation,” Potts said. “I’m looking forward to driving the organization as we relentlessly deliver to enable customer success”
As COO, Potts will work closely with Alphacore’s staff and expert advisory board and closest partners to ensure the organization can continue to adapt to serve customer needs as it significantly grows and expands commercially. In this role Potts’ will drive execution to continue delivering customer success with Alphacore’s innovative high-speed data and imaging solutions.
About Alphacore
Alphacore Inc., founded in 2012, is located in the innovative Silicon Desert of Arizona’s technology center is known for its innovations in rigorous data conversion microelectronics. Our verified highspeed, low power data conversion IP products available on latest technology nodes optimize time-tomarket for demanding commercial or radiation tolerant specifications.
Our engineering and leadership team combines long histories of delivering innovative data converter, radio-frequency (RF), analog and mixed signal products, and complete imaging systems for critical systems, through business success at companies from multi-nationals to startups. Our design team includes seasoned “Radiation-Hardened-By-Design” (RHBD) experts, and we specialize in designing high performance converter microelectronics, and reliability or authentication tools for niche needs of demanding segments, including scientific research, aerospace, defense, medical imaging, and homeland security.
|
Related News
- Sean Fan Joins Rambus as Chief Operating Officer
- Arteris IP Welcomes Back Veteran Laurent Moll as Chief Operating Officer
- Synopsys Appoints Sassine Ghazi as Chief Operating Officer
- Michael Boukaya Promoted to Chief Operating Officer of CEVA, Inc.
- MoSys Appoints Thomas Riordan as Chief Operating Officer
Breaking News
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- Breaking Ground in Post-Quantum Cryptography Real World Implementation Security Research
- RIKEN adopts Siemens' emulation and High-Level Synthesis platforms for next-generation AI device research
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
Most Popular
- Eighteen New Semiconductor Fabs to Start Construction in 2025, SEMI Reports
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Imagination pulls out of RISC-V CPUs
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY
- RISC-V in AI and HPC Part 2: Per Aspera Ad Astra?
E-mail This Article | Printer-Friendly Page |