USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm, 6nm)
DDR5 Ecosystem Ramps Up
By Gary Hilson, EETimes (November 1, 2021)
Like all iterations of DRAM, DDR5 will need an ecosystem of supporting technologies for it to become dominant, even as advanced workloads drive memory bandwidth requirements.
Rambus Incorporated is already laying the groundwork for DDR5 implementations more than a year away. The company recently announced it is sampling its 5600 MT/s 2nd-generation DDR5 registering clock drivers (RCD) to the major DDR5 memory module (RDIMM) suppliers. John Eble, vice president of product marketing for memory interface chips, said it will be several years before systems will be hitting the market. However, supporting technologies such as its RCD need to be evaluated and qualified by customers now so the ecosystem is ready to provide the bandwidth and capacity that will be required in next-generation data centers.
A DDR5 RCD along with data buffers (DB) are used in DDR5 Registered DIMMs (RDIMMs) and DDR5 Load Reduced DIMMs (LRDIMMs) to deliver higher bandwidth, performance, and capacity when compared to unbuffered DIMMs. RDIMMS, and LRDIMMs to reduce load on the CPU and improve the signal integrity of the command/address bus. The role of the RCD is as a key control plane chip which distributes Command/Address signals and clock to the DRAM devices on the DIMM. Rambus’ RCD can support DDR5 LRDIMMs when paired with 10n DB chips per module and reduces the effective load on the data bus to enable higher-capacity DRAMs on the module without reducing latency.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Rambus Inc. Hot IP
Related News
- Rambus Expands Portfolio of DDR5 Memory Interface Chips for Data Centers and PCs
- Global Semiconductor Sales, Units Shipped Reach All-Time Highs in 2021 as Industry Ramps Up Production Amid Shortage
- Rambus Advances Server Memory Performance with the Industry's First 5600 MT/s DDR5 Registering Clock Driver
- Chiplet Ecosystem Slowly Picks up Steam
- Rambus and Riscure Team Up to Deliver Best-in-class Security Testing Platform for Side-channel Analysis
Breaking News
- IAR Systems fully supports the brand-new Industrial-Grade PX5 RTOS
- Axiomise Accelerates Formal Verification Adoption Across the Industry
- Fluent.ai Offers Embedded Voice Recognition for Cadence Tensilica HiFi 5 DSP-Based True Wireless Stereo Products
- intoPIX to feature TicoXS FIP technology for premium 4K & 8K AVoIP wireless AV at ISE 2023
- Sevya joins TSMC Design Center Alliance
Most Popular
- Weebit Nano nears productisation, negotiating initial customer agreements
- Cadence Quantus FS Solution, a 3D Field Solver, Achieves Certification for Samsung Foundry's SF4, SF3E and SF3 Process Technologies
- Sevya joins TSMC Design Center Alliance
- Avery Design Systems and CoMira Announce Partnership To Enable UCIe-Compliant Chiplet Design
- Open Compute Project Foundation and JEDEC Announce a New Collaboration