D&R Upgrades IP Interconnect Web Portal in Cooperation with Toshiba America Electronics Corp. and Sonics

March 17, 2003 - Design & Reuse today announced a substantial upgrade to the IP Interconnect section of its popular Design and Reuse IP Web Portal. This new section will highlight key IP interconnection technologies and methodologies that enable fast, efficient and reusable connection between major IP blocks in a SoC design.

"This new and improved section reflects the growing importance of IP Interconnect technology in successful SoC design," points out Gabriele Saucier, D&R board chairperson. "D&R provides a significant effort in updating the community about design platforms and follows very carefully any interconnect initiative," adds Saucier. "It is our mission to give the largest coverage to innovative interconnect technologies. We are pleased to have such industry leaders as Toshiba and Sonics join us in creating an information rich inteconnect section for the SoC design community."

This new emphasis on IP interconnect technology reflects a growing awareness within the design community of the importance of IP interconnect tools and IP to the successful implementation of complex SoCs. In the past, the focus was on key "star" IP blocks, primarily processors, co-processors and DSP units and how application specific or function specific IP would work with those elements. The industry now recognizes that reusability, reliability, and time to market issues require a better approach. This new Design and Reuse IP Interconnect web portal section will provide an authorative source for information about IP interconnect strategies, tools, methodologies and interconnect IP.

"Our aggressive SoC programs depend upon rapid integration of a wide range of basic and complex IP blocks," said Richard Tobias, vice president of the ASIC and Foundry Business Unit at Toshiba America Electronic Components, Inc. (TAEC). "This new portal will give the industry a resource where they can learn about new and more effective technologies for managing the IP interconnect portion of SoC development. The interconnect is a fundamental part of any system. At TAEC, we are using interconnects like OCP and AMBA to speed up design time and get our customers to revenue quickly with complex SoC designs."

"Our commitment is to the development of interconnect IP and related technology that speed the SoC development process," states David P. Lautzenheiser, Vice President of Marketing at Sonics, Inc. "This new web portal reflects the growing industry awareness of the importance of IP interconnect to the success of SoC-based products. We envision a future where interconnect IP technology becomes a primary means for reducing SoC development costs, improving system performance, enabling design reuse and improving time to market."

The new IP Interconnect web portal section will highlight and promote general purpose interconnection technology and promotes initiatives such as OCP IP, the Sonics customizable and synthesisable interconnect system and innovative platforms such as the TAEC SoCMosaic (TM) custom chip program.

About Design And Reuse
Design and Reuse is the leading web portal for IP and SoC exchange, and the first worldwide provider of intranet/internet XML-based IP reuse and IP supply chain design software called IP/SoC Manager Series. Founded in September 1997 in Grenoble, France, D&R now has operations that extend to Europe, North America and Asia. For more information on Design and Reuse, please visit the website at www.design-reuse.com or send an email to info@design-reuse.com . Telephone (headquarters): +33-4-76706487; Fax: +33-4-76706453.