Tool suite supports reconfigurable processor

Tool suite supports reconfigurable processor
By Richard Goering, EE Times
August 14, 2001 (12:57 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010813S0079

SUNNYVALE, Calif. — Claiming to provide the first development environment for a reconfigurable signal processor, Chameleon Systems this week will announce C-Side (Chameleon Systems Integrated Design Environment), a tool set for its CS-2112 reconfigurable communications processor (RCP).

C-Side uses a combined C language and Verilog flow to map algorithms into the chip's reconfigurable processing fabric (RPF). Chameleon introduced the CS2112 earlier this year. The chip won't be in full production until the fourth quarter, but the tools are being made available now so designers can start application development.

"So far as we are aware, we are the only reconfigurable processor supplier that has taken the path of providing tools to the customer so they can build their own custom algorithms," said Tim Erjavec, vice president of marketing for Chameleon.

The tool set lets users map algorithms into the CS2112's RPF, which includes four slices, each of which can be reconfigured independently. Each slice has three tiles, and each tile includes seven 32-bit data-path units (DPUs), two multipliers, four local-store memories and a control logic unit.

C-Side also provides programming and debugging for the chip's ARC processor core, which provides top-level management of chip resources for a given reconfiguration. Offering a higher level of granularity than FPGAs, the CS2112 allows reconfigurability at the microarchitectural level. That lets users reload slices with algorithms without having to work at a bit level. The architecture purportedly offers more flexibility than standard DSPs because CS2112 users can specify both functions and interconnect between functional units.

The C-Side tool set includes an optimized GNU compiler for the ARC core, an optimized Verilog synthesizer for the RPF, an interactive floor planner, an instruction-set simulator and a unified debug environment for the ARC core and the RPF. It comes with a development board that includes a single CS2112 along with memory, a PCI interface and a programmable I/O module.

Familiar methodology
Users start the design process with a C language description of their signal processing algorithms. They write a testbench and run an initial simulation on the ARC core. Then users identify data-path-intensive blocks, called kernels, which are targeted to the RPF. Users create functions for those blocks in Chameleon's assembly-like design entry language, which generates standard Verilog descriptions.

Raj Karamchedu, Chameleon's senior marketing manager, said the company plans to allow design entry from such tools as Matlab or SPW. That will let users draw data-flow diagrams in lieu of writing code. Until then, users must recapture portions of their C program in Verilog, because there's no direct translation between the two.

To program the DPUs, users wire together library elements ranging from adders and multipliers to FIR fi lters and Viterbi decoders. Those blocks are currently fixed, but Karamchedu said Chameleon is working to parameterize them. Control logic is programmed with Verilog state machines.

Chameleon's V2B (Verilog to bits) synthesizer takes the Verilog descriptions all the way to a placed-and-routed bit stream. While placement and routing are automatic, C-Side includes an interactive floor planner that lets users view a complete map of the chip's slices and tiles, get estimates of routability and manually rearrange the placement.

As a given kernel is programmed, the user brings the bit stream back into the ARC testbench, replacing the original fixed-point C model. A utility called eBios inserts calls in the testbench that allocate slices, load the kernel into slices, activate the configuration and execute the kernel. The testbench that includes the eBios calls is compiled using a GNU C compiler and is downloaded into the CS2112 development board.

While the Verilog kernel descriptions can be verified on any standard Verilog simulator, C-Side also includes ChipSim, an instruction-set simulator for the Chameleon architecture. It models the entire chip, including the ARC core and the RPF, using the GNU Debugger front end. Users can view all memories and registers on the CS2112, including the ARC core, and can single-step to debug the kernel.

'Real hardware debug'
A feature called VCD Dump lets users capture debug information from the internal nodes and registers of the CS2112 from both the development board and ChipSim. "Either way you get real hardware debug," Karamchedu said.

The development board also lets designers connect multiple RCPs to other devices in the system using the PCI bus or programmable I/O pins.

Karamchedu acknowledged a "learning curve" for designers unfamiliar with reconfigurable logic but said that a typical design cycle for a basestation, now 12 to 18 months, can probably be reduced to six to eight months using C-Side and the CS2112.

C-Side sells for $25,000 on Solaris platforms. The development board sells for $5,000.