SAN MATEO, Calif. IP Semiconductors A/S (Soeborg, Denmark) next week will release SpeedRouter, a network processor delivered as an intellectual-property core for Xilinx Inc. field-programmable gate arrays.
IP Semi is hoping that SpeedRouter will prove to be the first full-duplex OC-48 (2.5-Gbit/second) network processor on the market. Whether an FPGA implementation is accepted in the nascent market for network processors is yet to be seen, however.
The company chose to make SpeedRouter a core in order to increase flexibility, allowing the user to create a processor only as large as necessary for a particular router, said Jeppe Jessen, chief executive of IP Semi.
The SpeedRouter cores are designed for Xilinx's Virtex II or Virtex-E devices. Generally the core takes up only 33 percent of a Virtex II chip, leaving overhead for adding features or complex routing rules, Jessen said. At its most complex, SpeedRouter can handle 50 packets co ncurrently 25 in the ingress path and 25 in the egress path and the chips can be cascaded for added processing power.
"We have people talking about ten-tuple lookups [for every] packet, so there's a need for cascading multiple devices," Jessen said.
SpeedRouter is programmed by the user for whatever type of processing is required. At boot-up, the host CPU downloads the necessary binaries to SpeedRouter. It also uses SpeedRouter as a conduit for downloading the appropriate instructions to SpeedAnalyzer.
SpeedRouter appears to be the first FPGA-based network processor, but as such, it may require more user programming than most other off-the-shelf NPUs. While the device provides basic packet-forwarding functions, it's up to the user to program functions such as key extraction and packet modification, said Bob Wheeler, senior analyst with research firm The Linley Group (Mountain View, Calif.).
"There are a lot of pieces left to the customer," Wheele r said.
SpeedRouter was designed for a cut-through data path, as opposed to the store-and-forward nature of most pipelined architectures. Data in the Speed-Router is shuttled through a series of delay engines, each one stopping the packet long enough for a table lookup to proceed. The idea is to keep performance steady by not having to store the packet in memory at every stage.
The goal of avoiding any store-and-forward activity is another reason the part is being implemented in an FPGA.
Packets aren't stored in memory until they leave SpeedRouter and go to an external traffic-management chip, which queues them for transmission to the switch fabric. SpeedRouter provides the scheduling info to send the packet to the switch fabric, meaning the chip does not require a particularly intelligent traffic manager, Jessen said.