Verisity's Specman Elite Version 4.1 Boosts Verification Reuse

Latest Release Rich with e Reuse Methodology Features that Enable Coverage-Driven Verification up to the System- and Platform-Level

MOUNTAIN VIEW, Calif., Mar 24, 2003 (BUSINESS WIRE) -- Verisity Ltd. (Nasdaq:VRST), the leading supplier of essential technology and methodology for functional verification, today announced the immediate availability of version 4.1 of the Specman Elite(R) testbench automation solution. The latest release of the company's flagship product includes e Reuse Methodology (eRM(TM)) features that increase the power of eRM compliant e Verification Components (eVCs) to generate and synchronize complex multi-transaction scenarios, including sequences, new visualization and consistent message reporting. In addition, Specman Elite v4.1 contains significantly enhanced performance features that provide significant improvements in test generation and co-simulation performance.

eRM is a complete reuse methodology that codifies the best practices for pre-verified IP. eRM delivers a common e Verification Component (eVC) usage model, and ensures that all eRM compliant eVCs will interoperate seamlessly regardless of origin. eRM is an important component of Verisity's proven coverage-driven verification (CDV) methodology. Only a CDV methodology provides a complete solution that scales with design complexity, provides predictable results and enables verification reuse.

"As more demands are put on engineers to deliver better products faster, verification teams are using IP for their SoC, system and platform-based verification to get their products out the door. This has caused a dramatic increase in the use of multiple eVCs in each design," said Francine Ferguson, vice president of corporate and strategic marketing. "eRM and the new powerful features delivered in Specman Elite version 4.1 make eVCs the only verification reuse technology capable of meeting engineers requirements. This is what the industry needs today and is what will enable verification teams to meet the increasing trends of SoC, system and platform-based designs."

"We are committed to deliver our licensees with high quality products where verification of the cores and the subsystem plays a major role," said Erez BarNiv, vice president of R&D at ParthusCeva. "With time and resources stretched to the limit, a methodology that lets us reuse components of our environment as well as incorporate eVCs is an important issue high on our priority list. By following a coverage-driven verification approach, we know that we're using a complete solution that will be effective on our next project. We believe that CDV and eRM is the right direction for engineers looking to address productivity and quality." ParthusCeva is the leading provider of a broad range of licensable DSP cores and SoC DSP Subsystems, including XpertTeak(TM), PalmDSPCore(C), Teak(C) and TeakLite(C).

New eRM features Enable Coverage-Driven Verification

By following the eRM guidelines when developing eVCs, engineers are encapsulating the advantages of a CDV methodology in their eVCs and enabling smooth reuse at all levels of abstraction as eVCs developed for verification at the block level can be easily reused at the chip and system level. This not only saves significant amount of time -- because engineers don't need to re-architect their verification environment -- but it gives them a methodology that scales with their design.

The recent eRM enhancements in v4.1 include: -- Sequences -- Sequences enable consistent scenario generation within the verification environment. Rather than generate each item atomically, test developers can now easily generate scenarios of multiple transactions and control them over time. At the system/platform level, multiple eVCs are commonly employed. Sequences allow for the creation of system-level scenarios that generate and synchronize sequences across all the eVCs. -- Visualization -- New visualization tools and unified message handling make the debugging process consistent and simpler for eVC integrators and test writers. -- Messages -- The Message feature enables users to have strict control over the information being reported in the verification environment. Users are given control over the appearance of message alerts concerning the operation of models. The user is able to dictate which models are silent, which ones are on, and which level of messaging is provided. Pricing and Availability

Specman Elite v4.1 is available now on the Linux Operating System, Solaris and HP workstations running HP-UX. The price is $50,000 U.S. for a floating LAN license.

About Verisity

Verisity, Ltd. (Nasdaq:VRST), is the leading supplier of essential technology and methodology for the functional verification market. The company addresses customers' critical business issues with its market-leading software and intellectual property (IP) that effectively and efficiently verify the design of electronic systems and complex integrated circuits for the communications, computing, and consumer electronics global markets. Verisity's Specman Elite(R) testbench automation solution automates manual processes and detects critical flaws in hardware designs enabling delivery of the highest quality products and accelerating time to market. The company's strong market presence is driven by its proven technology, methodology, and solid strategic partnerships and programs. Verisity's customer list includes leading companies in all strategic technology sectors. Verisity is a global organization with offices throughout Asia, Europe, and North America. Verisity's principal executive offices are located in Mountain View, California, with its principal research and development offices located in Rosh Ha'ain, Israel. For more information, visit www.verisity.com.

Note to Editors: Verisity, Specman Elite, and eRM are either registered trademarks or trademarks of Verisity Design, Inc. in the United States and/or other jurisdictions. All other trademarks are the property of their respective holders.