RISC-V-based AI IP development for enhanced training and inference
San Diego's PTSC seeks money for patented variable clocks with MPUs
San Diego's PTSC seeks money for patented variable clocks with MPUs
By Semiconductor Business News
August 3, 2001 (4:36 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010803S0076
SAN DIEGO -- Embedded microprocessor technology developer Patriot Scientific Corp. today announced plans to begin collecting licensing fees for patented systems and methods that use variable-speed clocks with processors. The publicly-traded San Diego company said several of its patents are now being used by a "significant number" of developers in microprocessor and digital signal processor markets. The company's patented approach to variable-speed clocks and processors is called "JUICEtechnology." "On behalf of PTSC, we are just beginning to license JUICEtechnology and are inviting device manufactures and users of embedded processors to work with us to enhance, under appropriate licenses, the value of their products, which incorporate this critical technology," said R.G. Blum, chairman and chief executive officer of Patriot Scientific. He said a legal search of the marketplace showed that many companies have incorporated features, "which app ear to fall within the scope of PTSC's rights." "The development of these intellectual property strategies is being coordinated with the advice of our outside counsel Knobbe, Martens, Olson and Bear, LLP," Blum said. PTSC did not say how many companies would be contacted for licensing negotiations or how much money it was seeking for access to the patents.
Related News
- Swiss-Based Enclustra Announces US Operations in San Diego to Realize the Full Potential of Embedded Chip Technologies
- oneNav's Patented pureL5 GNSS Solution Proven in Silicon
- VESA Launches Industry's First Open Standard and Logo Program for PC Monitor and Laptop Display Variable Refresh Rate Performance for Gaming and Media Playback
- Mixel's Patented D-PHY RX+ IP Extends Market Share with Automotive Microcontrollers
- SmartDV's LPDDR5 IP Clocks 612 MHz in FPGA Functional Test, 1.6GHz at 28nm
Breaking News
- RISC-V in AI and HPC Part 2: Per Aspera Ad Astra?
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Creonic Introduces Doppler Channel IP Core
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY
- RISC-V in AI and HPC Part 2: Per Aspera Ad Astra?
Most Popular
- Imagination pulls out of RISC-V CPUs
- Eighteen New Semiconductor Fabs to Start Construction in 2025, SEMI Reports
- BrainChip Brings Neuromorphic Capabilities to M.2 Form Factor
- RISC-V in AI and HPC Part 1: Per Aspera Ad Astra?
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY
E-mail This Article | Printer-Friendly Page |