Creonic Introduces Microchip FPGAs as Supported Technologies
Kaiserslautern, Germany, July 11, 2022 – Creonic GmbH, the market leader in IP cores for satellite communications, today announced general support for Microchip FPGAs. IP cores can now be provided for low-power families such as PolarFire® and IGLOO® 2, SoC FPGAs like PolarFire SoC and SmartFusion® 2 SoC and furthermore radiation-tolerant devices such as RT PolarFire and RTG4™.
In particular in space applications, low-power and radiation-tolerant FPGAs are very popular. As such, Microchip FPGAs are widely adopted in this domain. Based on customer demand, Creonic introduced the Microchip tool flow with the Libero® SoC Design Suite, being able to deliver a good deal of its portfolio for the Microchip FPGA ecosystem. Where needed, features like Error Detection and Correction (EDAC) of the built-in SRAM-based RAM blocks are exploited.
Customers benefit from access to the broad IP core portfolio covering standards like CCSDS, DVB-S2/DVB-S2X and DVB-RCS2. These are first choice for satellite communication and further near-earth or deep-space applications. Forward Error Correction (FEC) algorithms covered are Turbo, LDPC, Polar, RS, BCH, and convolutional coding.
About Creonic GmbH
Creonic is an ISO 9001:2015 certified provider of ready-for-use IP cores for several algorithms of communications such as forward error correction (LDPC, Turbo, Polar), modulation, and synchronization. The company offers the richest product portfolio in this field, covering standards like 5G, 4G, DVB-S2X, DVB-RCS2, DOCSIS 3.1, WiFi, WiGig, and UWB. The products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. For more information please visit our website at www.creonic.com.
|
Creonic Hot IP
Related News
- Microchip FPGAs Speed Intelligent Edge Designs and Reduce Development Cost and Risk with Tailored PolarFire® FPGA and SoC Solution Stacks
- Functional Safety Certification Packages for Microchip FPGAs Speed Time to Market
- CAES Introduces Family of Radiation Hardened NOR Flash Memories for Space FPGAs
- Mid-Range FPGAs Reach the Next Power and Performance Milestone for Edge Compute Systems
- Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |