Elevate your High-speed data transmissions to the next level for all Display interfaces with the MIPI D-PHY/ LVDS Combo PHY IP Cores in 40nm

September 5, 2022 – T2M^IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s mature and silicon proven MIPI D-PHY/LVDS Combo PHY IP Cores in 40nm in major Fabs along with matching Controller IPs. The MIPI/ LVDS combo Core has been in multiple productions resulting in low power chipsets with very reliable data transmission.

The MIPI D-PHY/ LVDS Combo PHY IP Cores is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be easily fabricated and implemented in a GVI, LVDS or MIPI DSI system. The DPHY/LVDS Combo PHY IP cores is able to function as a D-PHY or LVDS according to the need of the user. For GVI/LVDS system, Macro consists of multi-transmitter channels and one SU unit. The transmitter macro can be configured to GVI (CML) or LVDS mode. For MIPI D-PHY system, the configuration includes a Clock Lane Module and four Data Lane Modules.

The MIPI D-PHY/ LVDS Combo PHY IP cores comes, enabled with DC coupling for the DPHY and LVDS and an AC coupling for the GVI. It can handle 10-bit/9-bit/8-bit/7-bit parallel interfaces per lane along with 0~9dB programmable 2-tap FFE (Feed forward equalization). The DPHY IP cores can also support One Clock Lane Channel and four Data Channels that is Bi-directional with Low-Power RX and Low-Power CD. The IP Cores supports the following data rates, GVI: 0.5Gbps~4.0Gbps; LVDS: 0.25Gbps~2.0Gbps;

D-PHY IP Cores: 187.5Mbps~1.5Gbps (High speed) and 10Mbps (Low Power).

The D-PHY/LVDS Combo PHY IP cores in 40nm has a shared PLL for all lanes and can create, stabilise, modulate-demodulate, filter, or recover signals from a channel that is noisy and is prone to loss of data. The Combo PHY is equipped with Embedded BIST can also be supported in wire bonding package. The IP Cores has a configurable reference clock frequency and boasts a very conservative power consumption that allows for individual power down for each lane.

MIPI D-PHY/LVDS Combo PHY IP cores along with has been used in semiconductor industry’s Smartphones, Automotive Camera, digital TVs, handheld computers, personal computers, Virtual Advertisement Screens, and other industrial uses…

In addition to MIPI D-PHY/LVDS Combo PHY IP Cores in 40nm, T2M ‘s broad silicon Interface IP Cores Portfolio includes USB, HDMI, Display Port, MIPI (DSI, CSI, UniPro, UFS, RFFE, I3C), PCIe, DDR, 1G Ethernet, V-by-One, programmable SerDes, OnFi and many more, available in major Fabs in process geometries as small as 6nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M: T2M^IP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com

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