MONTEREY, Calif. Three challenges for 90 nanometer designsleakage power, signal integrity, and design for manufacturing (DFM)are solvable, but require new design approaches, according to David Lan, methodology manager for TSMC in North America.
In a keynote speech at the Electronic Design Processes (EDP-2003) workshop here, Lan revealed how the giant foundry is tackling these concerns.
"At 0.25 microns, there are good tools, but as you move to 90 nanometers, noise, electromigration, IR drop, leakage power and DFM all become very severe,î" Lan said. "Ninety nanometers is a turning point."
Leakage power at 90 nm consumes almost as much as dynamic power, Lan said, requiring a new design flow to minimize leakage power. The crux of TSMC's flow is the use of Vt (voltage threshold) to trade off between power and speed. Low Vt cells are faster, but have more leakage power. High Vt cells are slower and have less leakage power.
For a recent 90-nm RISC core, Lan said, a low Vt library ran at 360 MHz but dissipated 21.6 mW in leakage power. A high Vt library dissipated 1.3 mW, but ran at 200 MHz. The solution, Lan said, was a mix of high, low, and nominal Vt cells, which in this case produced 9.7 mW of leakage power but still ran at 360 MHz.
How the cells are swapped is important, Lan noted. He said TSMC goes through synthesis, placement and routing with low Vt libraries, and then waits until after design-rule checking to swap low Vt cells for nominal and high Vt cells wherever possible. "Many tasks are not timing critical, so there will be a good percentage you can swap,î"he said.
For crosstalk, TSMC uses three approaches: prevention, analysis, and repair. One useful prevention technique is to set a maximum transition time to prevent weak victims. He said 0.6 to 0.8 nanoseconds works well for TSMC at 0.13 microns. During post-placement, techniques like slew balance, congestion removal, gate up-sizing and buffering can be use d. But, Lan noted, routing is more effective than placement in crosstalk reduction.
For analysis, TSMC uses Cadence Design Systems' Celtic product. Repair is done with Cadenceís First Encounter or Nanoroute tools, or Synopsys' Astro. Most timing and glitch violations can be fixed in around three iterations, but Lan noted that "there is usually something that can't be handled in the tool. We have a script to solve those problems."
Managing IR drop is a harder problem. "Today, we don't see that there is a good tool to handle this situation," Lan said. TSMCís approach is to use de-coupling capacitors to reduce IR drop. These are evenly distributed on power strap grids, with distribution based on power consumption.
DFM is a significant problem, and it has many dimensions, Lan said. These include process variation modeling, metal over via enclosure, redundant via insertion, dummy outside diffusion (OD) and metal insertion.
Intra-die process modeling is important because sheet resistance, thickness and width can all vary, producing interconnect delay differences as high as 40 picoseconds, Lan said. For inter-die process modeling, the challenge is defining the right process corners. Resistance-capacitance (RC) max/min corners check long paths, while capacitance (C) max/min corners check short paths, Lan noted.
If space allows, using larger or redundant vias can improve yields, Lan noted. He said that both Astro and Nanoroute now support this feature, and that it doesn't make timing worse. Designers can also add dummy metal, but should extract and check capacitance, he said.
Lan said that a TSMC reference flow that documents some of these effects will be available to customers on-line in May. "Design companies, foundries, and EDA companies all need to work together at 90 and 65 nanometers," he said.