4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
CEO Interview: Stephen Fairbanks of Certus Semiconductor
Trained as a semiconductor Analog and RF Circuit Designer, Stephen Fairbanks has been designing and developing process-specific I/O and ESD libraries for 24 years. His foundational training began while attending Brigham Young University designing highspeed 32 GSPS data acquisition systems and RF interfaces for a time-of-flight mass spectrometer. Soon after, he joined Intel, where he became the lead developer of the ESD and I/O libraries for what was then Intel's wireless, cellular, and mobile computing groups. He led the development of the I/O and ESD used on the initial generation and subsequent generations of wireless components for Intel Centrino chipsets and StrongARM cellular platforms. He was personally responsible for the ESD development and I/O support for three families of cellular communications processors and four families of handheld applications processors.
Leaving Intel in 2006, he became an ESD and I/O consultant, establishing SRF Technologies and Certus Semiconductor. Several of his most notable efforts were assisting companies to find ESD solutions for groundbreaking, first-generation technologies. These include but are not limited to ESD protection strategies on many of Qualcomm’s (Atheros) early generation RF front ends for cellular platforms; Inphi, Intel, Xilinx, and Freescale's (NXP) first generation 10, 28, and 56 GBPS interfaces, and many of Synaptic's early generation Touch-Screen Interfaces IC's and Touch-Display IC's.
Certus Semiconductor has the only commercially available production-proven high-voltage ESD solutions (-18V to 30V, including a 100V pk-to-pk RF Switch) in standard Low Voltage 3.3V, 2.5V, and 1.8V CMOS, for 40nm and below process nodes. These unique solutions have enabled several customers to interface NFC, high-voltage analog, and MEMS I/O’s directly, into low-voltage standard CMOS processes.
At Certus, Stephen has developed ESD process design rules, ESD libraries, and I/O libraries in logic, RF, mixed-signal, and high-voltage BCD processes at the 0.25um, 0.18um, 0.13um, and bulk-CMOS processes 90nm, 65nm, 45/40nm, 28nm, 22nm, 16nm, 12nm, 11nm, and 5/7nm processes. Stephen is familiar with several specialty processes, including HV BiCMOS, flash memory, SiGe, FD-SOI, SOS, and InP.
What is Certus Semiconductor's backstory?
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