Grenoble, France, March 9, 2023 -- Defacto Technologies just announced SoC Compiler 10.0, the new Major Release of its Front-end design solution for large SoCs.
This SoC Compiler 10.0 Major Release is addressing key SoC design challenges pre-synthesis.
The first challenge is the input format for internal and external IPs by taking full benefit from Accelera’s IP-XACT and RTL at different design steps. For example, when inserting connectivity both formats are fully supported with no disconnect between high level architecture decisions and implementation design decisions. With SoC Compiler 10.0 Major Release, it becomes natural and smooth to consider IP-XACT to describe a higher level of abstraction of the system and take advantage of bus interfaces while keep using RTL to describe the functionality, the hierarchy, and the complexity of the design. In summary the tool provides full flexibility between such formats even for non-IP-XACT users, from system level architecture to RTL implementation.
The second addressed challenge is related to the RTL generation process. With “ifdef” support, now RTL designers can generate generic and configurable RTL code. This also reduces the pain when maintaining large RTL databases.
The other key addressed challenge is the management of design collaterals such as UPF and SDC jointly with RTL and IP-XACT. A much higher degree of automation is provided with the tool 10.0 Release; either during the generation phase or when files need to be updated. Coherency checks with the RTL have been extended.
Last but not least, with full object-oriented APIs, Python users will find in the 10.0 Major Release a native support of the language to easily script and extend in-house applications on top of the tool.
Finally, Defacto's SoC Compiler 10.0 is not only about new capabilities and a higher degree of automation, it is also about better performance where several built-in features have been improved to offer rapid execution for large SoCs.
Several privileged Defacto customers are already taking benefits of SoC Compiler 10.0 and this version is now available for evaluation and production use. We’ll be very happy to assist you and make your design tasks more efficient!
More information can be found on our website: https://defactotech.com/
About Defacto’s SoC Compiler
Defacto’s SoC Compiler is a complete SoC integration platform multi-dimensional and pre-synthesis with a high level of automation taking into consideration all the design information including RTL, IP-XACT, timing constraints, power, physical and test. Before logic synthesis, SoC Compiler enables full implementation capabilities towards IP and connectivity insertion, design editing, views generation with real time monitoring of the integration progress. This enables SoC creation in minutes and maximizes design reuse from existing projects. In addition, several APIs are provided (Tcl, Python, C++, Java, etc.) to help in the development of internal and custom design platforms.
About Defacto Technologies
Founded in 2003, Defacto Technologies is a chip design software company providing breakthrough System on Chip design solutions to enhance design integration, design verification and also the Signoff of IP cores, subsystems and large SoCs.
By adopting Defacto’s SoC Compiler design solutions, major semiconductor companies are continuously moving from traditional and painful SoC design tasks to a fully automated design methodology. The related ROI has been proven for hundreds of projects.