Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies
Cadence 112G-LR SerDes silicon proven in GUC’s HBM3/GLink/CoWoS platform
April 26, 2023 -- SAN JOSE, Calif.— Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence® 112G-LR SerDes is silicon proven on the HBM3/GLink/CoWoS platform from Global Unichip Corp. (GUC). This milestone in the companies’ ongoing and successful collaboration solidifies Cadence’s leadership in high-performance connectivity IP for the high-bandwidth, high-reliability products that power the most advanced cloud data centers.
GUC’s big-die CoWoS platform represents real-world CPU, GPU, AI, and networking chips by integrating multiple instances of the Cadence 112G-LR SerDes with a 7.2Gbps HBM3 controller and PHY, as well as a GLink-2.5D die-to-die IP in the TSMC N7 process. Cadence collaborated with GUC on the interposer design to meet the strict high-speed signal integrity (SI) and power integrity (PI) requirements of 112G-LR SerDes signaling through silicon (CoWoS-S) and organic (CoWoS-R) interposers. The 112G-LR SerDes has been validated in the GUC CoWoS platform, demonstrating excellent performance and robustness in large-scale AI/HPC/networking chip conditions.
“Our AI/HPC/networking platform on TSMC’s CoWoS® technology meets high-power and high-speed requirements at the system level and demonstrates our industry leadership in delivering complete advanced packaging solutions,” said Igor Elkanovich, CTO at GUC. “Cadence’s robust, production-quality 112G SerDes was instrumental in allowing us to unleash new potential for scalable, multi-die AI, HPC and networking solutions.”
“The successful demonstration of the Cadence 112G-LR SerDes in GUC’s platform using TSMC’s CoWoS technology is a great example of design ecosystem collaboration on 2.5D multi-die packaging solutions,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Cadence’s leading IP solutions together with TSMC’s advanced technologies enable system-level innovations for AI/ML, HPC and networking applications.”
“Our successful collaboration with GUC exemplifies how Cadence is delivering SoC design excellence through our Intelligent System Design strategy,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “The Cadence 112G-LR/ELR PAM4 SerDes IP portfolio has been widely adopted by customers to enable AI, HPC, networking and 5G SoC designs. This milestone expands our collaboration, enabling GUC to prove their groundbreaking CoWoS platform and solidifying Cadence’s leadership in high-performance connectivity IP offerings.”
The Cadence 112G-LR SerDes incorporates industry-leading analog-to-digital converter (ADC) and digital signal processor (DSP) technology that delivers exceptional long-reach performance with superior margin and optimized power and area. The IP provides multi-rate support including 112/56Gbps in PAM4 mode, as well as 56Gbps and lower data rates in NRZ mode. The IP supports both standard and advanced packaging technologies.
The 112G-LR SerDes IP is part of the broader Cadence IP portfolio and supports the company’s Intelligent System Design Strategy, enabling SoC design excellence. For more information, please visit www.cadence.com/go/112gpr.
About Cadence
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at www.cadence.com.
|
Cadence Hot IP
Related News
- GUC Tapes Out AI/HPC/Networking Platform on TSMC CoWoS Technology Validating 7.2 Gbps HBM3 Controller and PHY, GLink-2.5D and 112G-LR SerDes IPs
- GUC Announces 2.5D and 3D Multi-Die APT Platform for AI, HPC, Networking ASICs
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- GUC Tapes Out Complex 3D Stacked Die Design on Advanced FinFET Node Using Cadence Integrity 3D-IC Platform
- GUC Taped Out 3nm 8.6Gbps HBM3 and 5Tbps/mm GLink-2.5D IP using TSMC Advanced Packaging Technology
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |