Creonic Introduces 25 Gbit/s LDPC IP Core Solution for ITU G.9804.2 PON Standard
Kaiserslautern Germany -- May 10, 2023 - Creonic GmbH, a leading IP core provider in the field of satellite communications, today introduced its latest LDPC forward error correction solution for passive optical networks (PON). The ITU G.9804.2 standard targets PONs with higher speeds when compared to previous generations. It specifies the common transmission convergence (ComTC) layer.
With the release of these new IP cores, Creonic is providing its customers with a high-performance solution that meets the demands of modern passive optical communication systems.
The Creonic ITU-25G PON LDPC Encoder and Decoder work as part of the Forward Error Correction (FEC) in the ComTC layer, and support the default coding scheme LDPC (17280, 14592), along with the optional scheme LDPC (17152, 14592).
The IP cores achieve throughputs of 25 Gbit/s. By running two cores in parallel a speed of up to 50 Gbit/s can be achieved. AXI4-Stream interfaces for data and configuration allow for a seamless integration int the customer design.
The LDPC decoder and encoder IP cores are available for licensing immediately, supporting ASIC and FPGA technologies such as AMD Xilinx and Intel.
Conntact us for more information.
|
Creonic Hot IP
Related News
- Creonic GmbH Introduces Advanced 5G LDPC Encoder IP core for Enhanced Mobile Broadband Connectivity
- Creonic Introduces FEC IP Core Solution for SDA Free-Space Optical OCT V3.0 Standard
- Creonic to Supply New LDPC Decoder and Encoder IP Cores for CCSDS Standard
- LSI Introduces Its First Standard Product System-on-a-Chip for Hard Disk Drive Manufacturers
- BroadLight Leads GPON Silicon Market With 25 Design Wins for Its Industry-Leading GPON Solution; BroadLight Extends Its Leading ITU-T PON Position in North America Into Countries Around the Globe
Breaking News
- TSMC September 2024 Revenue Report
- Crypto Quantique teams up with Attopsemi to simplify the implementation of PUF technology in MCUs and SoCs
- Intel, TSMC to detail 2nm processes at IEDM
- SensiML Expands Platform Support to Include the RISC-V Architecture
- MIPI Alliance Announces OEM, Expanded Ecosystem Support for MIPI A-PHY Automotive SerDes Specification
Most Popular
- Deeptech Keysom completes a €4M fundraising and deploys the first “no-code” tool dedicated to the design of tailor-made processors
- Bluetooth® V6.0 Channel Sounding RF Transceiver IP Core in 22nm & 40nm for ultra-low power distance aware Bluetooth connected devices
- Secure-IC unveils its Securyzr™ neo Core Platform at Embedded World North America 2024
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Electronic System Design Industry Posts $4.7 Billion in Revenue in Q2 2024, ESD Alliance Reports
E-mail This Article | Printer-Friendly Page |