Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Morpho Technologies demonstrates MPEG-4 video for 2.5G and 3G wireless applications
San Francisco, April 23, 2003 - Morpho Technologies continues to redefine the Digital Signal Processor with the demonstration of its 100 percent software MPEG-4 video codec for 2.5G and 3G Wireless multimedia applications at the Embedded Systems Conference, April 23rd through 26th, 2003.
One of the most significant applications and market drivers for 2.5G and 3G wireless communication is multimedia, specifically, digital video. The MPEG-4 video codec, the newest among many previous multimedia standards, allows low bit-rate compression/decompression of digital video data, as required in 3G wireless multimedia applications. Real-time streaming video, video-conferencing, and video-messaging require significant signal processing power. The ability to share this processing power with other applications within the mobile terminal allow for significantly reduced power consumption and silicon cost.
Morpho Technologies' MS1 reconfigurable Digital Signal Processor (rDSP) Cores implement the complete MPEG-4 baseband processing in software while simultaneously performing applications such as WCDMA, 802.11a/b/g, GPS as well as others. The MS1 rDSP Cores execute these applications by running programs residing in flash memory outside the core. The MS1 architecture is optimized for mobile terminal applications including digital video and baseband physical layer processing. Many functions have been implemented on the MS1 family of rDSP Cores, including DCT, IDCT, Motion Estimation and Compensation, Pixel Interpolation, CDMA Chip and Symbol Rate Processing, Error Correction including Viterbi and Turbo Codecs, and many others. These functions are available to Morpho's customers to use in their own designs that take advantage of the MS1 architecture.
Morpho Technologies currently has two versions of its MS1 architecture, the MS1-64 and MS1-16, available in test silicon available for customer evaluation. The MS1 rDSP Cores are available to customers as soft and hard IP cores as well as within the Morpho Technologies Development Systems.
"Morpho continues to develop products to meet the ever increasing embedded signal processing demands of 2.5G and 3G wireless applications. The MS1 rDSP supports the rapid implementation of applications in software that have traditionally only previously been available in hard-wired ASICs, comments Todd Nash, vice president, Business Development, Morpho Technologies. "For example, the MS1 provides a complete software solution for multimedia terminals including the physical layer and media processing without the need for separate signal processing paths in silicon. This can significantly reduce silicon area, power consumption, and development time."
Morpho Technologies will be demonstrating both the MPEG4 Codec and WCDMA baseband processing solutions running in real-time on development systems in booth 620 within the SoC Pavilion at the Embedded Systems Conference, April 23rd through 26th, 2003, at the Moscone Convention Center, San Francisco, California.
|
Related News
- VIA Telecom Licenses ParthusCeva TeakLite DSP Core to Power Next Generation 2.5G and 3G Wireless Modems
- Allegro introduces world's first H.264/MPEG-4 AVC High-Profile/High-Definition Hardware Video Encoding IP
- Tensilica Ports MPEG-4 BSAC Decoder for Digital Multimedia Broadcasting (DMB) to HiFi 2 Audio Engine
- New ARC Player Subsystem Combines Audio and MPEG-4 Video Functionality for Low Cost Consumer Devices
- Hantro announces next generation 4200 MPEG-4 / H.263 software encoder for ARM based wireless devices
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |