How the Worlds of Chiplets and Packaging Intertwine
By Majeed Ahmad, EETimes (September 26, 2023)
Chiplets mark a new era of semiconductor innovation, and packaging is an intrinsic part of this ambitious design undertaking. However, while chiplet and packaging technologies work hand in hand to redefine the possibilities of chip integration, this technological tie-up isn’t that simple and straightforward.
In chip packaging, the bare chip die is encapsulated in a supporting case with electrical contacts. The case protects the bare die from physical harm and corrosion and connects the chip to a PCB. This form of chip packaging has existed for decades.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- ARM pushes chiplets and 3D packaging for Neoverse chips
- How Arm Total Design is built around 5 key building blocks
- Faraday Unveils 2.5D/3D Advanced Package Service for Chiplets
- QuickLogic and YorChip Partner to Develop Low-Power, Low-Cost UCIe FPGA Chiplets
- A methodology for turning an SoC into chiplets
Breaking News
- Top 10 Foundries Experience 7.9% QoQ Growth in 3Q23, with a Continued Upward Trend Predicted for Q4, Says TrendForce
- JEDEC Publishes New CAMM2 Memory Module Standard
- UMC Reports Sales for November 2023
- Intrinsic ID Launches First Hardware Root-of-Trust Solution to Meet Functional Safety Standards for Automotive Market
- Global Semiconductor Sales Increase 3.9% Month-to-Month in October; Annual Sales Projected to Increase 13.1% in 2024
Most Popular
- Gartner Forecasts Worldwide Semiconductor Revenue to Grow 17% in 2024
- Intel to place US$14 billion orders with TSMC, says report
- BrainChip Attracts Former Intel AI Sales Executive to Head Up Sales
- Canonical joins the RISC-V Software Ecosystem (RISE)
- USPTO announces Semiconductor Technology Pilot Program in support of CHIPS for America Program