8051 instruction set compatible CPU soft core includes on-chip, real-time monitoring and debug capability, and is designed for implementation in Actel ProASICPLUS* re-programmable FPGAs
PLANO, Texas, May 07, 2003 -- QuickCores announces the industry's first (and only) FREE 8051 CPU soft core based on a JTAG-accessible, real-time monitoring and debugging architecture, and designed specifically for implementation in Actel's ProASICPLUS* family (i.e., APA family) of re-programmable FPGAs. The FREE license comes with the purchase of both QuickCores FLASH-232+ (or FLASH-USB+) APA device programming/debug pod, and a QuickCores BoxViewTM high-level "C" language debugger. The FREE license is restricted for use in Actel APA075 (3072-tile) FPGA's only. For use in larger Actel APA family FPGAs, other brand FPGAs, or ASICs, there is a modest, restricted use, licensing fee.
Dubbed the Pro8051+TM, the CPU soft core is 100% machine-code compatible with the industry standard 8051, and is based on a patented, real-time monitor architecture that allows non-intrusive, on-the-fly examination and modification of internal and external data memory, registers, and program memory using the ProASICPLUS existing JTAG pins, and without the requirement of any special monitor subroutines on the target side. This JTAG-accessible, real-time monitoring debug capability is "built in" and is considered extremely valuable by developers of real-time motor control and instrumentation applications because it allows them to essentially open up a magic window into their application and not only monitor precisely what their microcontroller is doing at any given instant, but also allows them to change the values/settings of any register, data, program, or external memory location on-the-fly by way of QuickCores JTAG, APA device programming/debug pod and BoxView high-level "C" language debugger.
The Pro8051+ CPU was designed specifically for implementation in Actel ProASICPLUS brand FPGAs in that it takes full advantage of available resources such as embedded dual-port RAM blocks, dynamically re-configurable embedded PLL block, and user JTAG block. By employing the ProASICPLUS embedded RAM blocks not only as data and program memory, but also as indirect pointer registers, a fully customized 8051-instruction-set-compatible microcontroller can be implemented in a FPGA as small as an APA075 (3072 tiles), complete with 2 kbytes of program RAM, 256 bytes of data RAM, three 8-bit parallel I/O ports, and on-chip, JTAG-accessible, real-time monitoring and debugging capability.
Based on a modified Harvard model, the QuickCores Pro8051+ is a single-clock, two-stage instruction pipeline design that executes instructions at least twelve times faster than the industry standard 8051 operating at the same input clock frequency. When implemented in an Actel APA075 (standard speed grade), the Pro8051+ is capable of instruction execution rates in excess of 12 MIPS. This is essentially equivalent to an industry standard 8051 operating at 144 MHz input clock frequency.
Using any of Actel's "Platinum", "Gold" or "Silver" versions of its Libero Integrated Design Environment (IDE) software packages, designers can easily create 8051- instruction-set-compatible microcontrollers customized to meet the functional requirements of their application. Customization is done at the top level of the design by editing the example special function register (SFR) module and instantiating it, along with the Pro8051+ module and appropriate size program RAM block module, at the top level of the design. Once the top level Verilog source file is modified and synthesized, it is ready to import into the Actel Designer tool for placement and routing. Within Designer, pins are physically assigned, device routed, and the resultant STAPL file generated. The finished product is a STAPL file that is used by either the FLASH-232+ or FLASH-USB+ device programming/debug pod to program the ProASICPLUS FPGA and thus create a customized 8051-instruction-set-compatible microcontroller.
The FREE Pro8051+ license comes with the purchase of both QuickCores FLASH-232+ (or FLASH-USB+) APA device programming/debug pod, and QuickCores BoxViewTM high-level "C" language debugger. The prices of the FLASH-232+ and FLASH-USB+ pods are $99 and $299, respectively, and each comes with an installation CD containing (1) STAPL player; (2) synthesizable Verilog RTL source code for the Pro8051+ CPU soft core, with example SFR blocks and top level design; and (3) a fully functional evaluation copy of the BoxView high-level "C" language (Pro8051+) debugger. The price for the BoxView Pro8051+ debugger is $499. Delivery is from stock. The FLASH-232+ and FLASH-USB+ programming pods and STAPL player software each come with a 30-day, money-back guarantee.
QuickCores develops and licenses synthesizable microcontroller IP for embedding in FPGA and ASIC devices. All of QuickCores microcontroller IP is built on a patented real-time monitor and data exchange architecture that enables high speed exchange and monitoring of data between target and host using a JTAG interface.
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* ProASICPLUS and Libero are trademarks of Actel Corporation.