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Platform supports assertions in software and hardware
By Richard Goering, EE Times
May 9, 2003 (4:02 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030509S0041
SANTA CRUZ, Calif. — Aldec Inc. has announced that its Riviera-IPT verification platform supports assertions in both software and hardware-assisted simulation, promising a speedup of 10 to 50 fold over traditional simulation. Riviera-IPT accepts VHDL, Verilog, and SystemC, and claims to accommodate up to 12 million FPGA gates or 3 million ASIC gates. Riviera-IPT offers both a software simulator and an accelerator. The Aldec assertion compiler produces RTL module checkers that are added to the synthesizable portions of the design. Riviera-IPT can then use these assertion checks at the behavioral level in the software simulator, and at the structural level in the hardware accelerator. The hardware-based assertion monitors consist of two parts: logical sequence of signals to be observed, and the desired response when the assertion violation is detected. Once implemented and verified, assertions ca n remain as part of the final design and used as real-time protocol checkers for detecting violations during normal device operation. With Riviera-IPT, designers verify one block at a time, first running software simulation and then synthesizing the block into the accelerator's FPGA hardware board. Other portions of the design can stay in the software simulator. Ultimately, most of the design blocks, including assertions, will reside in hardware, while behavioral testbench and SystemC constructs stay in software, according to Aldec. Riviera-IPT is available today for Unix, Linux, and Windows environments starting at $128,000.