San Jose, Calif., May 12, 2003-- Altera Corporation (NASDAQ: ALTR) today announced the availability of INTEC Systems' SONET/SDH intellectual property (IP) cores through the Altera Megafunction Partners Program (AMPPSM). Delivering increased flexibility, performance and time-to-market advantages in the development of optical networking products, these IP cores target Altera's high-performance Stratix™ device family, the industry's most powerful FPGAs. This compelling combination allows engineers to quickly develop a variety of data transport solutions for the movement of local, metro, and storage area network traffic over existing SONET/SDH infrastructures.
"The metro optical network infrastructure is based on SONET/SDH because it provides a reliable transport mechanism and well-established management procedures, all based on industry-standard and proven technologies," said Dr. Dennis Kong, CEO of INTEC Systems. "During the past 15 years, carriers have deployed SONET/SDH equipment worldwide, and our IP cores are building on that technology to continuously support the rapidly changing metro service requirements."
The INTEC IP cores include frame-mapped generic framing procedure (GFP-F), transparent-mapped GFP (GFP-T), and high-order virtual concatenation (HO VCAT) cores. INTEC's GFP cores enable the movement of various data protocols--including fast Ethernet, gigabit Ethernet, fibre channel, FICON, and ESCON--existing SONET/SDH networks. Additionally, by dynamically adjusting transport channel capacities, the HO VCAT core facilitates a highly efficient use of bandwidth.
"Customers utilizing INTEC IP and Altera's Stratix FPGAs will be able to extend the value of widely deployed optical networks by facilitating the movement of various network protocols over concatenated channels that have been sized for the need. By slicing the bandwidth spectrum, designers can take full advantage of the capacity of optical networks to move a variety of data as efficiently as possible," said Craig Lytle, vice president of Altera's IP business unit.
About INTEC IP
INTEC's GFP-F core includes a GFP-F processor with built-in gigabit Ethernet (GbE) interface functions, including GbE media access controller (MAC) and physical coding sublayer (PCS) supporting SONET/SDH transport rates from 51.84 Mbps to 1.244 Gbps. The GFP-F core consumes approximately 8,400 logic elements (LEs) in a Stratix device.
The GFP-T core is designed to provide low-latency transport of various SAN protocols and GbE data streams. The GFP-T core consists of a GFP-T processor, an 8B/10B encoder/decoder, a 64B/65B encoder/decoder, a TBI interface, and utilizes about 7,200 LEs in a Stratix device.
The HO VCAT core supports standard link capacity adjustment scheme (LCAS), providing the right-sized channel for data transport with a bandwidth granularity down to STS-1/VC-3. The LCAS control mechanism is used to perform dynamic bandwidth adjustment for the virtual concatenation group (VCG), so that new services such as scalable Ethernet private lines can be created to increase network link utilization and minimize transport cost. The core provides an internal buffer to accommodate differential delays of up to 125-microseconds between members of the VCG, and an external memory interface to support differential delays that exceed one SONET/SDH frame period. The core targets Stratix and uses approximately 17,000 LEs in its implementation.
Pricing and Availability
INTEC's IP cores have been optimized for Altera's high-performance Stratix device family and are now available on the Altera® IP MegaStore™ web site for download and evaluation with Altera's OpenCore® free test drive IP evaluation program. Core pricing starts as low as $24,995 for a fully optimized Altera Stratix netlist.
Implementation of the GFP-T core consumes 40 percent of a Stratix EP1S20F672C7 device, yielding an effective cost of $34 when devices are purchased in 25K unit quantities at the end of 2003. When targeting Altera's HardCopy™ device family, designers can realize an additional savings of up to 50 to 70 percent. For more information about the cores, visit the Altera IP MegaStore web site at www.altera.com/ipmegastore.
About the Altera Megafunction Partners Program (AMPP)
The Altera Megafunction Partners Program, established in August 1995, was created to bring the advantages of design reuse to users of Altera programmable logic devices. AMPP is an alliance between Altera and developers of IP cores that encourages megafunction development. Altera provides technical information and training to the AMPP partners, who create and support IP cores targeted for Altera PLDs. Currently, there are over 30 AMPP partners offering more than 150 megafunctions. Customers may request a free evaluation of any of these cores through Altera's megafunction listings at www.altera.com/IPmegastore.
About INTEC Systems
INTEC Systems is a leading high technology design service company specializing in network access and transport technology development. INTEC's unique expertise in this area has led to the development of next-generation SONET/SDH intellectual property, which addresses framing, multiplexing, pointer processing, channel add/drop, cross-connect, multiservice access/transport, etc., for applications covering the OC-3/STM-1 to OC-192/STM-64 transmission rates. INTEC provides a variety of turnkey services for high-speed and high-performance sub-systems and systems developers, including custom IP cores, ICs, and hardware and firmware designs from technical specifications to working implementations. More information on INTEC Systems can be obtained at www.intec2000.com.
Celebrating its 20th anniversary this year, Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com.