1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
Motorola won't tinker with ARM instruction set
Motorola won't tinker with ARM instruction set
By Anthony Cataldo, EE Times
May 14, 2003 (7:00 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030513S0041
SAN MATEO, Calif. Motorola's semiconductor products sector will create run-time libraries and hardware accelerators for its ARM-based microprocessors but has no plans to deviate from ARM Ltd.'s architectural road map, the company has told EE Times. Motorola's decision not to add its own instruction set extensions to ARM processors is in sharp contrast to Intel Corp., which has added its own instructions to its ARM-based Xscale processor line. ARM has granted Intel and Motorola a special "architectural license" that permits them to customize the processor in ways that other licensees can't. While Intel raised questions about its compatibility to ARM when it introduced its Wireless MMX instructions for Xscale last year, Motorola has stressed that it wants to maintain software compatibility with other ARM chips on the market. "There are already concerns about compatibility now that Intel has Xscale," said Kyle Harper, strategic marketing manager for wireless data and software at Motorola's Semiconductor Products Sector in Austin. "Customers are embracing ARM because there are multiple sources of competing product lines and they need to be software compatible." Rather than devise its own instructions, Motorola said it is developing run-time libraries for future ARM-based products, which are sold under the i.MX brand. These libraries will act as programming interfaces that extend the architecture in a way that will not require a software programmer to compile their code differently than they have for ARM-based systems. "The way you will see us going forward with our architectural license will be in a collaborative way that assures the intellectual property and know-how we bring to bear is 100- percent compatibility with software for all Motorola's versions of the core as well as ARM Ltd.'s cores," Harper said. The use of run-time libraries enables Motorola to put its own stamp on its ARM processors without running the ri sk of breaking software compatibility, said microprocessor analyst Jim Turley. "It's kind of a half-step. You give the appearance of adding new features without actually building them into the hardware. You could back out of it completely. It's politely called hedging your bets," Turley said. Intel, however, is less concerned about software compatibility and more interested in offering its own unique technologies. While Xscale is nominally compatible with ARM, in practice software developers and tool providers have to tailor their code to exploit these features. Intel's Xscale "is completely compatible with every one else but it doesn't work the other way around because Intel has extra features that everyone else doesn't have," Turley said. "And once you taste that forbidden fruit you can't go back. You're kind of locked into Xscale and not ARM." Rather than tinker with the core processor architecture, Motorola said it will focus on developing co-processors and system-level solutions for its i.MX processors. Later this year, for example, it plans to introduce its next generation processor with a hardware accelerator for security features, Harper said. Going forward, Motorola will add hardware accelerators for graphics and multimedia as a way to enhance performance without excessively boosting clock frequency, which can hurt power consumption, Harper said. In this way, Motorola will follow in the footsteps of its Quicc and PowerQuicc lines of processors, which are based on the 68000 and PowerPC processor cores respectively. "People like PowerQuicc not because it has a PowerPC processor in the middle but because of what it has around it," Turley said. Plying its system level expertise to reduce power and develop new bus approaches is another approach the company will take. It will also work with ARM on architectural enhancements to future ARM cores, as it did for the L2 cache included in the ARM11 processor, Harper said. It's all part of Motorola's plan to make its mark on those p rocessor elements that fall just outside the ARM core. "That's where major leaps forward in power and performance advantages really lie from this point on," Harper said.
Related News
- Segars won't rock the ARM boat
- STMicro won't use ARM's 3-D core in Nomadik processor
- The Industry's First SoC FPGA Development Kit Based on the RISC-V Instruction Set Architecture is Now Available
- Trump Precedent Won't Chill M&A
- SiFive Joins Microsemi's New Mi-V Ecosystem to Accelerate Adoption of RISC-V Open Instruction Set Architecture
Breaking News
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
- Cadence Reports First Quarter 2024 Financial Results
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |