Consortium vows to simplify IP reuse in SoCs
![]() |
Consortium vows to simplify IP reuse in SoCs
By Richard Goering, EE Times
May 23, 2003 (8:34 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030523S0036
SANTA CRUZ, Calif. A group of EDA, silicon intellectual property (IP) and semiconductor vendors will announce the formation of a consortium at the 40th Design Automation Conference next month that will work to facilitate the integration of IP blocks into system-on-chip (SoC) designs, EE Times has learned. The consortium is believed to be working on ways to define "metadata" that goes beyond simple input and output information for IP blocks. Consortium members include ARM, Beach Solutions, Cadence Design Systems, Mentor Graphics, Royal Philips Electronics, STMicroelectronics, and Synopsys. They will hold a press conference Monday, June 2, at 4:00 p.m. at the Anaheim Convention Center, site of the Design Automation Conference. While consortium members declined comment, sources suggested that the consortium will seek to define a standard way to convey important information about IP blocks, such as clocks, signals, and test strategies. Such information, considered important by IP developers and integrators, is sometimes unavailable, and is not presented in any consistent way. The consortium's work may also allow users to track the IP in their designs, know when and how it was modified, and what tools were used to create or modify it, observers said. A preview of the consortium's work may have appeared at the Design Automation and Test in Europe (DATE) conference in Munich, Germany this past March, when Beach Solutions Ltd., a provider of tools for IP packaging and integration, announced a collaboration with Cadence Design Systems Inc. to deploy a schema technology based on the XML database format. The schema describes parameters and their associations with common design and verification data required for SoC designs. At the time, Beach announced that it had developed a schema that allows IP block s to be developed and maintained independently from SoC target implementations. "Beach and Cadence are already working with strategic customers and other parties on an advanced schema definition with a formal release expected in the second half of the year," Beach said in a statement released in March. Oddly enough, the new consortium is working apart from the Virtual Socket Interface Alliance, an industry group that is working on IP reuse standards and practices. Larry Cooke, vice president of business development for the VSI Alliance, said he thought the consortium would fit well with the "adoption groups" that the alliance is developing. "I think a consortium like this is indicative that there are problems in this industry that need to be solved," Cooke said. "We're pleased that key members of the industry are stepping up. We have been talking to them."
Related News
- Crypto Quantique teams up with Attopsemi to simplify the implementation of PUF technology in MCUs and SoCs
- Bluespec Joins The SPIRIT Consortium to Advance IP Reuse Interoperability Standards for SoC Design
- SPIRIT Consortium drives IP re-use and interoperability with release of specification
- Agilent claims breakthrough in 'test reuse' for SoCs
- Thalia joins GlobalFoundries' GlobalSolutions Ecosystem to advance IP reuse and design migration
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |