SAN JOSE , Calif., May 27, 2003 -- Toshiba America Electronic Components, Inc. (TAEC)* today announced two new versions of its TX49 family of MIPS-based™ reduced instruction set computer (RISC) microprocessors (MPUs). The new 64-bit MPUs, designated TMPR4955CFG-400 and TMPR4956CXBG-400, are fabricated with 90-nanometer (nm) complementary metal oxide semiconductor (CMOS) process technology and are based on the Toshiba Corporation (Toshiba) TX49/H4 core. Power consumption is only 0.6 watt (W) when operating at their maximum frequency of 400 megahertz (MHz); this is currently the lowest power consumption of any processor in this product category. Utilizing a 32-bit (TMPR4955CFG-400) or 64-bit (TMPR4956CXBG-400) SysAD bus interface scheme, the devices are targeted at embedded applications such as color laser beam printers, high-performance set-top boxes and networking devices that handle large amounts of graphics data.
"Toshiba continues to migrate its standard 64-bit MIPS® RISC processors to higher and higher frequencies for applications that require higher CPU performance while providing system interface flexibility. TMPR4955CFG-400 and TMPR4956CXBG-400 are Toshiba's first standard processors based on our industry-leading 90nm process technology. We were able to achieve 400MHz operating frequency in a smaller device size while holding power constant," said Shardul Kazi, vice president of the TX-RISC Business Unit at TAEC. "Customers tell us that they like having the ability to switch from earlier, lower-frequency versions to the new processors while keeping the same companion chip. System architects use our processors with either off-the-shelf SysAD-compatible chipsets to save development time or develop their own specific solutions around the SysAD bus with greater customization."
"We congratulate Toshiba, a long-time leader within the MIPS community, on bringing to market the latest in new and innovative MIPS-based products," said Jack Browne, vice president of worldwide sales for MIPS Technologies. "By manufacturing the popular TX49 64-bit microprocessor in 90nm, the 400MHz performance expands the range of served applications."
Since 1989, Toshiba has been developing high-performance TX-RISC series microprocessors based on technology licensed from MIPS Technologies, Inc. for use in embedded applications, including peripherals, digital information devices and network devices.
Key features of the microprocessors are as follows:
- Integrates Toshiba's latest 64-bit core CPU, TX49/H4, which is fabricated with 90nm CMOS process technology and operates at 400MHz.
- Incorporates a four-way set-associative, large-capacity cache memory (32K-bytes instruction cache and 32K-bytes data cache.)
- Integrates a floating point unit (FPU) that is separate from the integer logic unit and realizes higher performance by making it possible to perform integer operations and floating point operations independently.
- Utilizes a 32-bit (TMPR4955CFG-400) or 64-bit (TMPR4956CXBG-400) SysAD Bus with multiplexed address and data as a system interface in order to interface with other SysAD-compatible devices.
- CPU core contains a dedicated debugging support unit (DSU) and uses an external enhanced JTAG (EJTAG) interface to perform execution control, such as setting breakpoints and performing real-time analysis while running at the maximum operating frequency.
Pricing and Availability
Samples of TMPR4955CFG-400 and TMPR4956CXBG-400 are scheduled to be available in August 2003. Sample pricing is estimated to be $35.00 per piece in 100-piece quantities for TMPR4955CFG-400 and $45.00 per piece for 100-piece quantities for TMPR4956CXBG-400. Mass production is slated for the end of 2003.
Technical Specification Summary
|Part Numbers ||TMPR4955CFG-400 and TMPR4956CXBG-400 |
|Process ||90nm process, 6-layer copper interconnect |
|Operating Power Voltage ||2 power sources: 1.2 Volts (V) core voltage, 3.3V or 2.5V I/O voltage |
|Maximum Operating Frequency ||400MHz internal, 133MHz external |
|On-Chip Cache Memory ||Instruction Cache: 32K-bytes, 4-way set associative |
Data Cache: 32K-bytes, 4-way set associative
|Memory Management Unit ||On-chip translation-look-aside buffer, 48-double-entry |
|Floating Point Unit ||Single- or double-precision floating point operation |
|Debugging Support Unit ||EJTAG support |
|External Data Bus Width ||TMPR4955CFG-400: 32-bits bus width |
TMPR4956CXBG-400: Selectable 64-bits or 32-bits bus width
|Package ||TMPR4955CFG-400: Plastic QFP160 lead-free package |
TMPR4956CXBG-400: Plastic FBGA217 lead-free package
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, optical communication devices, displays and rechargeable batteries for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the third largest semiconductor company worldwide in terms of global sales for the year 2002 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's website at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.
Information in this press release, including product pricing and specifications, content of services and contact information, is current on the date of the announcement, but is subject to change without prior notice.
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