Tensilica's Xtensa core comes with 0-In checkers
![]() |
Tensilica's Xtensa core comes with 0-In checkers
By Michael Santarini, EE Times
July 16, 2001 (1:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010716S0057
In an effort to resolve the system-on-chip verification challenge, 0-In Design Automation has launched its Verification Intellectual Property (VIP) suite, which lets RTL core providers deliver 0-In checkers with their cores. First out of the gate is the new Tensilica Xtensa IV configurable processor, which will ship with 0-In checkers that can validate the core's interface logic. The checkers come without extra charge to the intellectual-property integrator; Tensilica customers don't have to license any software from 0-In. The VIP program helps both IP creators and integrators, said Curt Widdoes, 0-In's CEO. "IP creators derive a lot of benefit because their customers can integrate more quickly and have fewer problems during the integration," Widdoes said. "The user can quickly see problems with the way in which he communicates with the core. He has increased visibility and can find bugs that would be missed otherwise." Checkers con vert assertions into comment-based directives within RTL code that can run with any HDL simulator. Checkers that come with the Xtensa IV, for example, can help ensure that interface handshakes and transactions are working property, and that a user's assumptions about one-hot encoding, FIFOs and counters are not being violated. Widdoes said the 0-In checkers adapt to any processor configuration Xtensa IV users choose. They can, for example, change bus widths or inputs as the core is reconfigured. "Configuration makes it even more difficult for an IP provider to make sure a customer is complying with all specifications," he said. Widdoes said 0-In is talking to other core vendors about its VIP program, but declined to reveal names. 0-In is hoping IP integrators will buy some additional software. What they get for free, Widdoes said, is a version of the 0-In Check product that works only for the specific checkers that come with the core. If users want to add more checkers, or use the 0-In Searc h product to provide more thorough verification, they'll have to pay for it. See www.0-In.com. http://www.eetimes.com/
Related News
- 0-In's Archer Verification System Targets Verification Hot Spots
- Verisity, 0-In and Novas Announce Strategic 'VPA' Collaboration to Address Nanometer SoC Verification Challenges
- 0-In Design Automation to Present at Verisity's Worldwide Next-Generation Verification Seminar Series
- ClariPhy Licenses Tensilica's Xtensa Dataplane Processor (DPU) for Optical Networking Mixed Signal, Digital Signal Processing (MXSP) SOCs
- Chelsio Communications Licenses Tensilica's Xtensa LX Customizable Dataplane Processor Core for 10 Gigabit Ethernet
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |