SAN MATEO, Calif. Altera Corp. has devised a scalable, unidirectional interface for linking disparate I/O interfaces on its high-end programmable logic devices. The part is intended to shift the burden of linking different interfaces from designers who often must use on-chip buses for this task, to intellectual-property (IP) providers that must retrofit their cores with the interface.
The Atlantic interface was designed for Altera's Apex II devices, its latest crop of high-end programmable logic parts. The goal is to help FPGA designers cut out weeks of work that go into creating an on-chip bus or proprietary interface between cores.
Connecting two cores that have Atlantic bolted on will be as simple as drawing two lines between blocks in its FPGA editing software, according to Altera (San Jose, Calif.).
Atlantic can be configured as a point-to-point, point-to-multipoint, crossbar switch or as core logic. For the current-generation Ap ex II FPGAs, it can be scaled from 8 to 128 bits, allowing speeds from 155 Mbits/second to 40 gigabits/s.
Atlantic is being billed as an on-chip interface as opposed to an on-chip bus because it does not consider peripherals to be either masters or slaves and it functions without arbitration. Altera argues that a simple handshake is enough to pass data between cores at high speeds.
While buses like ARM's Amba are often used for that task, Altera thinks processor-oriented buses consume too much logic resources and introduce latency in FPGAs. "Processor buses have a lot of overhead and they're expensive to implement, especially considering the number of logic elements and memory they need. And they're not well-suited for the data path," said Justin Cowling, a senior manager with Altera's IP division.
When designers use IP from different sources, they often have to familiarize themselves with the local bus on each core and then design logic to reconcile the two. With Atlantic, "designers don't have to harass the IP vendors to learn about the local side buses in order for them to interoperate," said Altera product marketing engineer Eugene Ahn.
According to Altera, it takes several weeks of design work to stitch a couple of IP functions together. That is especially true for the aggregation and de-aggregation of signals. Using Atlantic, a designer making gear for a DSLAM can cull four POS-PHY 2 signals, each at 622 Mbits/s, over a single POS-PHY 3 interface running at 2.5 Gbits/s without having to create multiplexing logic.
The interface can also be useful for tying together different I/O standards.
"A designer can drop down a pre-optimized Flexbus and pre-optimized POS-PHY and draw a line between the two cores," Cowling said.
The key word here is pre-optimized. If Altera wants Atlantic to succeed, it will have to persuade intellectual-property providers to rework their IP code to make it Atlantic friendly.
Altera started bolting Atlantic onto its own I/O cores and is talking to var ious IP vendors. Its engineers are also finishing up a functional model of the interface. And it hasn't ruled out submitting the interface to the Virtual Socket Interface Alliance, where it could be considered for standardization.
"It will take some time to adopt Atlantic to their IP, but we're talking about taking the burden off the shoulders of the end customer," said Ahn of Altera.
So far, ModelWare Inc. has jumped on board with a pair of Flexbus Level 3 and 4 cores while Innocor Ltd. is developing an AAL5 SAR core. Altera now has several POS-PHY, Utopia, asynchronous transfer mode and point-to-point protocol cores that comply with Atlantic.
Rival FPGA vendor Xilinx Inc., however, doesn't see an urgent need from customers for a special interface. One option for Xilinx customers is to use the CoreConnect peripheral bus, a bidirectional bus with a single master and multiple slaves devised by IBM's PowerPC processor group. To Xilinx, FPGA designers are already adept at building their own interfac es or on-chip bus logic on FPGAs.
"It's trivial to make adaptations on the fly with FPGAs," said Mike Aaldering, senior developer of IP solutions at Xilinx. "You can take data in and make it wider and lower the clock rate or make it narrower. You've got the flexibility to decide how much logic it will take and what you're going to burn so you don't have to lock yourself into one thing. Nobody's screaming that they've got a problem."