Reduces tester cost, test generation time and test escapes
Anaheim, California, June 2, 2003. Genesys Testware, Inc., a leading supplier of embedded test solutions, today announced the introduction of HiertestMakerTM - a hierarchical test solution for logic and wiring in System Integrated Circuits (IC). HiertestMaker reduces tester cost, test generation time and test escapes in system ICs.
System ICs containing millions of transistors and thousands of pins exceed the capacity of most Automatic Test Equipment (ATE) increasing test application cost. Moreover, Automatic Test Pattern Generation (ATPG) tools take a very long time to process large system IC. This increases time to develop first working prototype and time for design changes.
System ICs also contain long wires that interconnect its major blocks. These global nets are highly susceptible to bridging faults. Traditional ATPG tools do not target bridging faults. This leads to large amount of test escapes in system IC manufacturing.
Multi-die packages containing system IC are widely used in weight and power sensitive applications like cellular phones. It is very difficult to test inter-die wiring after the package is assembled since there is no mechanical access. Flip-chip packages are attached to printed circuit boards (PCB) using solder balls on it's bottom surface. It is impossible to physically probe chip pins in flip-chip packages during PCB manufacturing. This makes it very difficult to test PCB wiring.
HiertestMaker solves all these problems using hierarchical boundary scan technology. It produces a top-level model of the design containing all sub-blocks, pads, boundary scan registers, clock generators and Test Access Port (TAP) controller. HiertestMaker produces circuits that are compatible with the IEEE 1149.1 standard. It is not necessary to add any new steps in the design flow since it replaces boundary scan insertion in current design flows. It also produces circuits that can control any embedded logic or memory test circuits in the system IC. HiertestMaker generates tests to detect and diagnose bridging faults in global nets. It generates tests to test chip pads independent of the core of the system IC. It also generates a complete Boundary Scan Description Language (BSDL) file for the system IC.
"Hierarchical test tools based on IEEE 1450.6 Core Test Language (CTL) for Sytems-on-chip (SOC) are over-kill for full-scan designs," said Bejoy Oomman, President of Genesys Testware. "SOC test tools from major EDA vendors are very difficult to due to their complexity. These tools also add another step in the design flow. Besides, hierarchical test tools from large EDA vendors are listed at nearly quarter million dollars annually. HiertestMaker offers an easy to use, efficient and affordable alternative for system IC designers".
HiertestMaker is available now. HiertestMaker starts at $40,000 for a one year subscription.
Genesys Testware, Inc. provides advanced hierarchical embedded test solutions for system integrated circuits. Its products are all silicon-proven in various customer designs. Genesys Testware's corporate headquarters are located at 76 Whitney Place, Fremont, CA 94539. For more information, please visit the company's web site at http://www.genesystest.com
HiertestMaker is a trademark of Genesys Testware, Inc. All other trademarks or registered trademarks are the property of their respective owners.