SANTA CLARA, Calif. Agilent Technologies Inc. on Friday (May 30) claimed it has made a breakthrough in "test reuse" for complex ICs, by rolling out a software management tool that supports the core test language (CTL) standard for chip-testing applications.
The company has also formed CTL alliances with Synopsys Inc. and STMicroelectronics Inc. Agilent's solution supports EDA tools from Synopsys, while STMicroelectronics is a beta site customer for the company's CTL technology.
Agilent's solution is basically a graphical software "browser" tool, which merges, manages and re-uses test programs and CTL data for its 93000 line of automatic test equipment (ATE). The technology promises to accelerate test development times, thereby lowering ATE costs, according to Palo Alto, Calif.-based Agilent.
The software tool, dubbed the SmarTest Program Generator CTL Browser, supports the emerging IEEE P1450.6 CTL standard. This standard, which has not been ratified by the IEEE, is a "superset" and a more robust version of the IEEE 1450 standard test interface language (STIL) technology for ATE, according to the company.
CTL could jumpstart the move to standardize test-interface languages for ATE. STIL has been around for years, but it has not been widely implemented by many ATE houses. Many ATE vendors continue to use their own proprietary ATE languages.
CTL itself enables a systems-level device to have "testable" cores. It provides a "standard" language for describing design-for-test (DFT) structures for IP cores in system-on-a-chip (SoC) designs.
It also encapsulates test data and provides syntax for each core, providing a key enabler for ATE: reusable test, said Tom Newsom, vice president and general manager of Agilent's SOC ATE Business. "The technology adds DFT capabilities to the 93000 test suite," Newsom said.
"It also creates the concept of reusable test. It enables you to take reusable cores and create reusable test [vect ors for each core]," he said in an interview with SBN at the company's ATE headquarters in Santa Clara.
Ultimately, the technology will accelerate IC-test times, he said. "I think it's a big deal," he said. "We think we have a profound technology [to enable] DFT."
In a technical paper from Agilent's beta-site customer STMicroelectronics, CTL also promises to bridge the gap between design and test. "ATE data, output in a P1450.6 compliant form, may be input to an ATPG tool for re-checking the forward translation path and any changes made on the fly by the tester user. After this validation, the tester generated P1450.6 data is made available for any re-use of the IP core," according to the paper from STMicroelectronics of Geneva.
Agilent's big CTL risk?
Agilent appears to be taking a big risk with CTL. The standard is not ratified, although many ATE vendors are evaluating the technology, said Phil Burlison, chief technical officer of Inovys Corp., an ATE startup (Pleasan ton, Calif.). "Everybody is thinking about CTL, Burlison said.
Analysts said Agilent is rushing CTL to the market in order to stay one step ahead of its competitors, especially its main rivalTeradyne Inc., according to analysts. Last year, Teradyne announced that Wave Wizard, its standard tool for test program generation provided by partner Test Insight, will support STIL.
Agilent's browser supports both STIL and CTL. Brower data can be viewed, manipulated and reused on an ATE workstation. The browser is a graphical digital pattern, timing, and test generation tool. Rather than translating files like most program generators, the browser manages the test development process for each port from data extraction to test generation.
The tool works in conjunction with Synopsys' EDA tool technologies, including its DFT Compiler, TetraMax, and SoCBist. Agilent's technology is in beta-site testing at STMicro. The browser from Agilent will be available in September.