PHY cell is sampling in TSMC 0.13-micron and available for licensing
Los Altos,CA - June 02, 2003 - Rambus Inc. (Nasdaq:RMBS), a leading provider of chip-to-chip interface products and services, today announced it has provided its customers with first samples of chips supporting the PCI Express(tm) interface. Rambus customers are using this chip to evaluate the RaSer(tm) physical layer (PHY) cell for PCI Express applications. The new chip can be combined with FPGAs, ASICs or other chips on PCI Express boards to be used for compliance and interoperability testing.
Rambus' PCI Express PHY evaluation chip is the first to be implemented on a TSMC 0.13-micron process and has been delivered to customers for system level testing. The chip supports four PCI Express lanes, to address x4, x8, x16 and x32-lane based PCI Express devices used in chipset, graphics, and switch-based applications for PCs, servers and communications systems. The chip meets PCI Express specifications, including the jitter requirements, and supports key functions such as Receiver Detect and Beacon Generate and Detect features.
"This chip is the first PCI Express silicon IP off our 0.13-micron process. Rambus has demonstrated its ability to deliver challenging serial interface technology on advanced processes. This early PCI Express silicon is key to enabling our customers to take advantage of the market's expected rapid adoption of the PCI Express standard," said Ed Chen, director of Design and e-Service marketing for TSMC.
TSMC leads the industry in 0.13-micron production, having taped out more than 230 product designs to its advanced 0.13-micron processes. With 100,000 plus eight-inch equivalent wafers already shipped, year-end 2003 production is projected to exceed 400,000 wafers. More than half of TSMC's 2003 0.13-micron capacity will be in 300mm-wafers.
Rambus has developed high-speed I/O solutions for its customers for over 13 years. This expertise, initially applied to the memory market, is now being applied to other chip interface markets such as PCI Express interconnects. Beyond high speed circuit design, Rambus' expertise includes signal integrity analysis, high speed package design, and board / backplane characterization as well as extensive modeling.
"We strongly believe in the importance of the PCI Express interface for next-generation chip interconnect applications," said Kevin Donnelly, vice president of the Logic Interface Division at Rambus. "We are seeing tremendous demand from our customers to bring PCI Express solutions to market quickly on TSMC's leading foundry processes."
The RaSer PCI Express PHY features low power consumption - 80mW power per lane - and a small die area. The RaSer PHY is based on a proven SerDes cell used in InfiniBand(tm)and Ethernet XAUI products. Rambus offers a configurable Physical Coding Sublayer (PCS) layer to provide customers a flexible interface to the PCI Express MAC and upper logic layers.
About Rambus Inc.
Rambus is a leading provider of chip-to-chip interface products and services. The company's breakthrough technology and engineering expertise have helped leading chip and system companies to solve their challenging I/O problems and bring industry-leading products to market. Rambus' interface solutions can be found in numerous computing, consumer electronic and networking products. Additional information is available at www.rambus.com.
Rambus is a registered trademark and RaSer is a trademark of Rambus Inc. PCI-SIG is a trademark of the Peripheral Component Interconnect Special Interest Group. All other trademarks are properties of their respective owners.