Altera Introduces Industry's First FPGA Floating-Point FFT IP Cores

New Cores Leverage Stratix Device Family's Embedded DSP Blocks to Deliver a Cost-Effective Floating-Point FFT FPGA Solution

San Jose, Calif., June 3, 2003--Altera Corporation (NASDAQ: ALTR) today introduced the industry's first fast Fourier transform (FFT) floating-point intellectual property (IP) cores for FPGAs. Altera's FFT floating-point cores are IEEE 754-compliant and optimized for the company's Stratix™ family of high-performance FPGAs. By leveraging the Stratix device family's embedded digital signal processing (DSP) blocks, Altera now offers designers a cost-effective floating-point FFT FPGA solution-a longtime goal of the FPGA industry. The new IP cores are intended to support designs for military, industrial, and medical systems that require powerful FFT processing capabilities.

"Our customers previously used either off-the-shelf standard products or multiple compute engines, such as the Altivec systems, to process our wide-band data," said Ralph Kimball, president of Echotek. "Going forward, Altera's floating-point FFT core, combined with the DSP and memory capabilities of the Stratix devices, will give our customers the processing power and flexibility they require for their military, radar, and signal intelligence applications."

Altera's new offering is available in two versions, Radix 2 and Radix 4 cores. The Radix 4 version delivers a 1 K points complex processing time of 25 microseconds at 200-MHz system speeds and uses only about 10 percent of the resources in a mid-range Stratix device. The Radix 2 is half the size of the Radix 4 and offers a 1 K points complex processing time of 50 microseconds at 200-MHz system speeds. Additional versions of the new cores are under development.

"Floating-point FFT cores offer considerable benefits in terms of dynamic range and simplified system design when compared with fixed-point FFT cores," said Martin Langhammer, Altera's chief scientist. "The Stratix DSP blocks, with their ability to directly support 36 x 36 multipliers at over 250 MHz, offer significant advantages in implementing floating-point functions."

Altera's floating-point FFT cores are parameterizable for transform length and use IEEE 754 single precision format (1 sign bit, 8 exponent bits, 23 mantissa bits) for both data and twiddle storage. The cores use IEEE 754 extended precision arithmetic (1 sign bit, 8 exponent bits, 31 mantissa bits) internally for greater data integrity. With up to 7 Mbits of on-chip memory, Stratix devices enable very large FFT implementations in internal memory, and both core versions support external memory interfaces to allow unlimited transform sizes.

Verified with ModelSim® software version 5.6A simulation and Quartus® II version 2.2 software native synthesis, the cores include a comprehensive set of MATLAB-based utilities to generate and analyze test benches for both ModelSim software-based simulation and Quartus II software version 2.2 synthesis. In addition to the FFT cores, Altera also offers a suite of free IEEE 754-compliant operators, including multipliers and adder/subtractors. The operators can support either single or extended format. An IEEE 754-compliant multiplier can be implemented in as little as a single Stratix DSP block and about 200 logic elements.

The development of the floating-point FFT core is part of Altera's Code:DSP initiative to extend the reach of FPGAs into a wide range of mainstream DSP-based applications. Highlighted by the industry's most advanced design flow supporting system design, hardware design, and software design, the Code:DSP initiative sharpens Altera's focus on the DSP market by offering designers a broad range of support services, tools, and development platforms for implementing reconfigurable DSP designs in leading-edge FPGAs.

Availability
Customer can request an OpenCore™ free "test-drive" of the Radix 4 and Radix 2 FPGA floating-point FFT cores through Altera's IP MegaStore™ web site located at www.altera.com/ipmegastore. A perpetual license for the cores is priced at $7,995, including 12 months of upgrades and support. The Altera® floating-point multipliers are included in the Quartus II software, which is priced at $2,000 for a 12 month license.

About Stratix Devices
The Stratix device family is the industry's first family of production-qualified FPGAs built on a 0.13-micron, all-layer copper process and the winner of EDN magazine's 2002 Digital IC Innovation Award. Featuring embedded DSP blocks, embedded RAM blocks, and support for leading-edge and emerging I/O standards, Stratix devices give designers the performance and densities they need to meet the challenges of high-bandwidth system design. For more information about the Stratix device family, visit www.altera.com/stratix.

About Altera
Celebrating its 20th anniversary this year, Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com.

Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. HyperTransport is a trademark of the HyperTransport Consortium. All other product or service names are the property of their respective holders.

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