Artisan Executives to Present at Conference Events
SUNNYVALE, Calif., -- May 29, 2003 -- Artisan Components, Inc., (Nasdaq: ARTI), a leading provider of physical intellectual property (IP), today announced it will debut its comprehensive analog, mixed signal and digital solutions at the Design Automation Conference (DAC), June 2 through 6, 2003 in Anaheim, California. Additionally, Artisan's executives will participate with leading companies in conference events including presentations on design-to-process integration, signal integrity issues and the impact of advance processes on COT design.
With the recent acquisition of Nurlogic Design, Inc. and the subsequent forming of its Analog/Mixed Signal Business Unit, Artisan combines products and in-house design expertise up to a system-level that provides a broad portfolio of IP solutions to accelerate system-on-a-ship design and production. Artisan's widely used memory, standard cell and general-purpose I/O libraries combined with its high-performance analog IP functions, specialty I/Os and high-bandwidth system-interface PHYs will be featured at DAC in Artisan's booth #1860 and demo suite #2682.
Artisan Executives At DAC
Mark Templeton, co-founder, president and CEO of Artisan will present "SoC Economics: Exploiting the Modern Semiconductor Landscape" daily in the Artisan demo suites. To register, please contact Artisan directly at email@example.com.
Jim Hogan, senior vice president of business development at Artisan will be a participant in a panel entitled: "Libraries: Lifejackets or Straightjackets?" This is a DAC panel session being held on Thursday, June 5, 2003 and is open to all conference attendees.
In addition, Artisan will be joining partners in panels and presentations throughout the show.
On Tuesday, June 3, 2003, Artisan will be co-hosting two events. The breakfast session is entitled "Design With Integrity!" in which Artisan, Synopsys and IBM will discuss providing signal integrity solutions for silicon success. A luncheon panel, co-hosted by Artisan, Mentor Graphics and TSMC, is entitled "Design-To-Process Integration: Crossing the 0.13-micron Bridge." Panel moderator, industry-recognized EE Times editor, Ron Wilson and the companies' panelists will explore 0.13-micron design and how foundry-qualified integrated design tools and building blocks make it easier today.
On Wednesday, June 4, 2003, Artisan and Cadence co-sponsor a breakfast meeting with the theme, "Enabling SoC Success for 130-Nanometers And Below."
Artisan will also join Synopsys in the Synopsys demo suite #2614 (Suite 9) to present "Artisan and Synopsys: Providing Solutions for Silicon Success, June 3 and 4. Pre-register at http://www.synopsys.com/links/dac_reg.html.
In addition, on June 2 through June 4, 2003, Artisan will participate in the Cadence sponsored Silicon Design Chain booth #1531 on the exhibition floor. For additional information on any of the events above, please contact Artisan by email at firstname.lastname@example.org.
About Artisan Components
Artisan Components, Inc. is a leading semiconductor intellectual property (IP) provider. The company's design platforms are licensed to over 1000 companies worldwide. Artisan's design platforms provide IC designers with a common interface to a range of process technologies from the world's leading foundries. Built on Artisan's Process-Perfect™ memory generators, standard cell and I/O libraries, Artisan's design platforms include a comprehensive set of views and models supporting leading design tools and methodologies. Artisan's worldwide network of EDA, IP and design service partners extend the Artisan standard to a complete set of system level design and integration solutions. Artisan is headquartered in Sunnyvale, California. More information about Artisan Components, including free library access can be found at: http://www.artisan.com.
Artisan Components is a registered trademark and Process-Perfect is a trademark of Artisan Components, Inc. All other trademarks or registered trademarks are the property of their respective owners.