GUC Taped Out UCIe 40Gbps IP using Adaptive Voltage Scaling (AVS)
Hsinchu, Taiwan – Jan 07, 2025 — Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced today that it has successfully taped out Universal Chiplet Interconnect Express™ (UCIe™) PHY IP with 40Gbps per lane on TSMC’s N5 process, beyond UCIe’s highest speed, for AI/HPC/xPU/Networking applications. UCIe 40G chiplet interface provides industry leading bandwidth density 1,645 GB/s per mm of die edge. The IP supports any speed up to 40Gbps and uses Adaptive Voltage Scaling (AVS) to reduce supply voltage achieving 2x better power efficiency for required speed. The chip is assembled using TSMC’s CoWoS® (Chip on Wafer on Substrate) advanced packaging technology.
Following suit GUC’s world first UCIe 32G solution readiness on TSMC’s N3P process in the industry in 2023, GUC further taped out UCIe 40G on the TSMC N5 process for meeting high bandwidth demand of multi-die integration at AI/HP/Networking applications. To further reduce PHY power, GUC features Adaptive Voltage Scaling (AVS), to optimize PHY supply voltage and driving strength, improving power efficiency by 2x. Minimal supply voltage and driving strength are selected by training algorithm to meet eye opening margins criteria ensuring robust operation in changing voltage and temperature conditions. The IP integrates silicon-proven proteanTecs’ I/O signal quality monitors. Signal quality is monitored in mission mode, during data transfer, without re-training or causing any data transfer interruption.
For easy integration, GUC developed bridges for AXI, CXS and CHI buses using UCIe Streaming Protocol. These bridges are optimized for high traffic density, low power, low data transfer latency and efficient end-to-end flow control, facilitating seamless transition from single chip NoC to chiplets architecture. The bridges support Dynamic Voltage and Frequency Scaling (DVFS) allowing digital supply voltage and bus frequency change on the fly while ensuring uninterrupted data flow. To support the IP integration in the bottom dies using TSMC’s SoIC®-X technology, it can be placed “face up” with adding TSVs for supplies and interface signals.
“We are thrilled to announce our new-generation UCIe IP supporting 40 Gbps with 2x better power efficiency,” said Aditya Raina, CMO of GUC. “We have established a complete silicon-proven 2.5D/3D chiplet IP portfolio at TSMC’s 7nm, 5nm and 3nm technologies. Together with design expertise, package design, electrical and thermal simulations, DFT and production testing for the TSMC 3DFabric®offerings including CoWoS®, InFO, and TSMC-SoIC®, we provide our customers with a robust and comprehensive solution, enabling fast design cycles and quick bring up of their AI/HPC/xPU/Networking products.”
“We are committed to delivering the fastest and the lowest power 2.5D/3D chiplets interface IPs, facilitating seamless transition from monolithic to chiplets architectures,” said Igor Elkanovich, CTO of GUC. “Convergence of 2.5D and 3D packaging using HBM3/4, UCIe and GLink-3D interfaces enables highly modular, much bigger than reticle size processors of the future.”
GUC UCIe Highlights
- 40Gbps per lane
- Bandwidth density: 1,645 GB/s per mm
- Adaptive Voltage Scaling (AVS) for 2x better PHY power efficiency
- AXI, CXS and CHI bus bridges
- Dynamic Voltage and Frequency Scaling (DVFS) for user parallel bus
- Per lane, in-mission mode I/O signal quality monitoring by proteanTecs
To learn more about GUC’s UCIe IP portfolio, and TSMC’s CoWoS® and SoIC® total solution, please contact your GUC sales representative directly or email guc_sales@guc-asic.com
About GUC
GLOBAL UNICHIP CORP. (GUC) is the Advanced ASIC Leader who provides the semiconductor industry with leading IC implementation and SoC manufacturing services, using advanced process and packaging technology. Based in Hsinchu, Taiwan, GUC has developed a global reputation with a presence in China, Europe, Japan, Korea, and North America. GUC is publicly traded on the Taiwan Stock Exchange under the symbol 3443. For more information, visit www.guc-asic.com
|
Related News
- GUC Taped Out UCIe 32G IP using TSMC's 3nm and CoWoS Technology
- GUC Taped Out 3nm 8.6Gbps HBM3 and 5Tbps/mm GLink-2.5D IP using TSMC Advanced Packaging Technology
- GUC Tapes Out Complex 3D Stacked Die Design on Advanced FinFET Node Using Cadence Integrity 3D-IC Platform
- Eliyan Supports Latest Version of UCIe Chiplet Interconnect Standard, Continues to Drive Performance and Bandwidth Capabilities to 40Gbps and Beyond to Help Meet the Needs of the Multi-die Era
- Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC's N3E Process Technology
Breaking News
- Baya Systems Raises $36M+ to Propel AI and Chiplet Innovation
- Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
- VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
- ARM boost in $100bn Stargate data centre project
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
E-mail This Article | Printer-Friendly Page |