Streamlined design system for RapidChip enables fast, predictable design of high-performance, complex platform ASICs
- Single design cockpit with integrated tool suite
- Rule-based methodology
- Automated, correct-by-construction tools
- Lowers cost barriers for highly complex chip design
MILPITAS, Calif., June 23, 2003 -- Extending its strong history of developing and delivering leading-edge design tools and methodologies, LSI Logic Corp. (NYSE: LSI) today introduced RapidWorx™, an innovative design system for the company's RapidChip™ platform ASIC products.
RapidWorx significantly reduces design obstacles for high-performance, custom silicon, making the design of RapidChip products fast, predictable and affordable for a broader range of markets. RapidWorx achieves this through the combination of a streamlined design flow, rule-based methodology and automated, correct-by-construction tools. Using RapidWorx, customers quickly achieve design handoff that allows LSI Logic to tape-out to manufacturing as fast as one million gates per week.
"LSI Logic is delivering RapidWorx to bring, for the first time, high complexity chip design to the masses," said Ronnie Vasishta, vice president, Technology Marketing and CoreWare Engineering, LSI Logic Corporation. "LSI Logic's customer focus demands that we deliver end-to-end solutions. RapidChip dramatically reduces the time to design with silicon platforms, a rich library of IP, and tools and methodology optimized for the platform."
The RapidWorx streamlined design flow consists of five basic steps: configuration of the RapidChip slice resources, physical mapping of those resources, RTL rule checking with physical RTL analysis, physical synthesis, and netlist handoff rule checking. Each step is executed by a tool launched within the RapidWorx cockpit. The tools are tightly integrated, enabling features such as cross-probing between tools.
RapidWorx is a rule-based design system that ensures first-pass success. RTL rule compliance is done early in the design cycle, preventing RTL problems that can only be fixed with changes in RTL code or synthesis strategy from propagating further into the design flow. The final gate-level netlist check prior to handoff ensures the one million gates per week layout cycle.
The RapidWorx design system avoids user and implementation errors with automated, correct-by-construction tools. Iterations between logical and physical design are avoided because design integrity and other physical issues are addressed automatically in the tools. Many design integrity issues are addressed in the pre-built RapidChip slices, removing them from the design flow completely.
RapidWorx customer engagements will start July 2003.
The RapidChip (http://www.lsilogic.com/products/platform/index.html) semiconductor platform combines the high-density, high-performance benefits of cell-based ASICs with the fast time-to-market and customization benefits of FPGAs, and the proven IP benefits of ASSPs. Targeting the Communications, Consumer and Storage markets, RapidChip uses LSI Logic's high-performance field-tested CoreWare® IP, customizable logic, embedded memory, and innovative design concepts to significantly reduce design and manufacturing risk and costs. RapidChip also provides a fast and seamless migration path to full standard-cell ASIC - driving unit costs even lower. Information on RapidChip technology is available through LSI Logic's direct sales channels and worldwide distribution partners.
About LSI Logic Corporation
LSI Logic Corporation (NYSE: LSI) is a leading designer and manufacturer of communications, consumer and storage semiconductors for applications that access, interconnect and store data, voice and video. In addition, the company supplies storage network solutions for the enterprise. LSI Logic is headquartered at 1621 Barber Lane, Milpitas, CA 95035, http://www.lsilogic.com.