Los Gatos, California – 1 July, 2003. TransEDA® PLC, (LSE: TRA) the leader in ready-to-use verification solutions, today announced the release of a PCI Express Verification Toolkit - a set of Verilog and C++ models that implement a variety of simulation-based environments for verifying that a design complies with the PCI Express revision 1.0a specification.
The toolkit consists of a PCI Express version 1.0a compliant Bus Functional Model (BFM), an integrated Protocol Checker, Symbol and Packet Trackers, and a highly configurable test bench that demonstrates how to use the tools and also provides a template for quick integration with an existing simulation environment. A supplied model driver also allows optional use with VN-Control – TransEDA's application specific test automation tool.
Features and uses
The BFM fully supports the Verilog HDL language and may be configured as either a root complex or end-point node. It may be configured to operate in parallel or serial symbol interface mode making it ideal for compliance testing, functional regression testing, performance analysis and system-level, pseudo-random testing with automated data checking.
The comprehensive and intuitive Verilog Application Programming Interface (API) allows the toolkit to be easily integrated into existing simulation environments and minimizes the work required to begin test development. The transaction, link and electrical layers provide both symbol and bit-serial interfaces of 1-32 lanes wide. The highly configurable model allows control over all aspects of operation, including error injection and reporting, and programmable root complex or endpoint behaviour as defined by the PCI Express 1.0a base specification
As an initiator, the toolkit can generate all types of transactions, messages and completions for Transaction Layer Packets (TLPs) and all types of Data Link Layer Packets (DLLPs). Full support is also provided for Quality of Service (QOS) verification using prioritized traffic channels and virtual channels. Full support for multiple-outstanding transaction generation and data checking, and precise control over transaction and packet attributes, including error injection, simplify the generation of complex test cases.
As a completer, the toolkit fully supports all memory spaces, including configuration space, and provides precise control over transaction completion - including error injection and reporting.
Rule-based protocol checking engine
The protocol checker provides extensible protocol verification and generates detailed, easy-to-read log files showing activity at the symbol and transaction levels
Integrating the Bus Functional Models with TransEDA's VN-Control test generator simplifies the generation of directed, pseudo-random and reactive pseudo-random test-cases. Working with this verification environment allows easy generation of complex corner-case situations and tests of the system's ability to deal with errors while running. Automatic collection of statistics and coverage information also aid the evaluation of test case effectiveness.
VN-Control support for other models, including TransEDA's HyperTransport, and PCI/PCI-X/PCI-X 2.0 models, and the ability to integrate third-party models, allows users to develop sophisticated system-level verification environments.