CHAMONIX, France -- While stressing that his paper at the Multiprocessing System-on-Chip (MPSOC) conference held here last week discussed a research project, John Goodacre, multiprocessing core manager at ARM Ltd. (Cambridge, England), disclosed some of the thinking at the company, which is, in essence, to offer a single core that comprises multiple ARM 32-bit processors, as a route to higher performance and power efficiency.
The number Goodacre used to illustrate his paper was four, to which ARM would add buses and logic to ensure each processor's level-one cache coherency, provide interprocessor communications and debug facilities, plus the logic to power down individual processors when not required. On the outside of the four-way 'super-core' would either be a single level-two cache plus main memory, or a direct link to main memory.
As much as possible the users would be insulated from needing to know how many processors were, "inside the b ox" so that it could be treated from the outside like a single high performance ARM instruction set machine, said Goodacre.
Goodacre said that the research project had now come to the stage where it is being opened up to ARM customers and third parties, such as operating system and compiler vendors, who would influence if and when ARM multiprocessing cores come to market and in what configurations.
Goodacre was presenting at last week's MPSOC, which was organized by Ahmed Jerraya of the TIMA Laboratory, Grenoble, France, and Wayne Wolf of Princeton University. The event is in its third year as a high-powered think-tank on what is possible and on what is likely to happen in system-on-chip (SoC) development. While much of the discussion at the conference was on high-level requirements for the better expression of parallelism and on how massively parallel processors could have an impact on performance, ARM's proposal is more incremental to established practice.
It also seems likely that ARM could start to advocate multiprocessing more strongly as its partners are already producing multiprocessing designs based on multiple ARM processor cores, but are forced to work without, for example, high-level language compiler support.
Goodacre told the conference that ARM is unlikely to stop at a four-way multiprocessing core. ARM is considering a hybrid symmetry model with support for both symmetric and asymmetric multiprocessing architectures.
Goodacre told SBN that a four-way symmetric multiprocessing core with ARM's traditional robust support and offering close to four times the performance of an ARM uniprocessor looked like it would appeal to partners who might chose not to push on to the most advanced, and costly, manufacturing process technology.
And others could chose to take the benefit of more advanced manufacturing in addition to the benefit of multiprocessing cores.
In contemporary manufacturing process technologies ARM 32-bit RISC cores take up so little die area that whether o ne or four is deployed makes little difference to the total functionality of the SoC or its die area and cost. Goodacre added that it had been shown that taking an application that runs on a 200-MHz clock frequency ARM core and splitting it between two ARM cores running at 100-MHz clock frequency could show a power efficiency benefit and for relatively low numbers the effect scaled well.
"We've been building an MP multiprocessing ecosystem for a while. Releasing MP-capable products. Partners are building lots of MP designs," said Goodacre in presenting his paper. "So now we are at the stage to work with the partnership to formalize MP support, introduce capabilities for SMP, make available a trial implementation of an ARM MP platform design for partner evaluation, feedback."
Both the ARMv5 and ARMv6 instruction set architectures include certain features to support some forms of co-processing and multiprocessing.
The ARM multiprocessing trial platform is a four-processor device with a single AM BA bus and a trigger and trace bus to help with debugging and system integration.
"According to our research four is a good number but if a particularly partner said a three-way or a five-way MP core is best for their applications, that is a configuration we would probably support," Goodacre said.
ARM could also produce heterogeneous cores with say three ARM processors and a DSP or two ARM processors, some dedicated hardware and a DSP, Goodacre said.
Goodacre declined to say which ARM processor the four-way multiprocessor demonstrator would be based on, and when asked if ARM had benchmarked the efficiency of any particular applications on an ARM multiprocessor model, he said not but that it was expected that, in line with previous research findings, dynamically adaptive chip-level multiprocessing should be up to twice as power efficient as the best-managed uniprocessor.
In April, ARM announced that it was working with LSI Logic Inc. and ParthusCeva Inc. to develop a specification that add resses the integration of DSP cores with ARM and other microprocessor cores in system-on-chip (SoC) designs. At the time ARM said the specification would be announced in the second half of 2003. This would appear to be related to ARM's multiprocessing initiative, although it concerns heterogeneous implementations.