SAN JOSE, Calif.--(BUSINESS WIRE)--July 14, 2003--Aptix Corporation, a leading producer of hardware and software platforms for pre-silicon prototyping of embedded System-on-Chip (SoC) designs, announced today that it has begun shipping Release 5.0 of its software for Aptix reconfigurable prototyping products -- System Explorer(TM) and Software Integration Station(TM) (SIS).
The new software release is immediately available to all customers with software support contracts, and includes new support for TCL scripting, improved probing and triggering, and new hardware self-test.
Raj Mathur, Director of Software Technical Marketing at Aptix remarked, "The 5.0 release has several key enhancements to both the logic and physical mapping flow that make it even easier for our customers to map and debug their design. Most notably, we now support TCL scripting, GTECH netlist flow and have introduced a flexible probe instrumentation flow in Design Pilot, our flagship logic-mapping tool." Mathur continued, "In the Explorer software, we've introduced a new hardware self-test program to help our users focus on debugging their design rather than debugging hardware faults. In addition, we've reduced the time-to-probe signals by up to 70%. These, along with other new capabilities, boost designer productivity and allow them to increase verification cycles while making the products much easier to use."
ST Among the First to Use
"With this release, the incremental probing time has helped me debug design signals much faster than before. Not only is the probing faster, but the software can spawn incremental re-compiles to several workstations now. They've also built a very powerful LINUX-based self-test program and we are pleased to see these key improvements," said Helena Krupnova, CMG Functional Verification Group, STMicroelectronics, Grenoble, France.
New Features in Release 5.0 Provide User Benefits
Design Pilot(TM) software enhancements
TCL support Benefit: Automation, predictable and faster flow for incremental changes
- Asynchronous clock Data Path Management (DPM)
Benefit: Reduce number of FPGAs or increase speed with increased visibility
- Flexible probe assignment (pre- and post-partition)
Benefit: Instrument probes during mapping to eliminate lengthy internal place-and-route time.
- Improved logic optimizer
Benefit: Powerful partitioning options to reduce number of FPGAs and, potentially, increase speed of system (e.g. 2x)
Explorer(TM) software enhancements
Improved virtual support
Benefit: Reduce time to setup virtual nets in FPGA modules (setup and incremental changes). Save hours of manual setup.
Easy trigger setup for multiplexed buses
Benefit: Reduce time to setup logic analyzer with complex trigger conditions for multiplexed signals. Save hours of manual setup.
New and improved self-test Benefit: Increased hardware coverage, reduced time to detect faults. Removes hardware setup debug time
- Fast internal probing (approx. 70% time reduction!)
Benefit: Reduce time to add probes
Pricing and Availability
Version 5.0 is available now. Aptix pre-silicon prototyping systems start at $60,000 (USD).
Acronyms and definition:
|FPGA ||Field Programmable Gate Arrays |
|GTECH ||Synopsys internal format |
|PSP ||Pre Silicon Prototype |
|SoC ||System on Chip |
|SIS ||Software Integration Station |
|TCL ||Tool Command Language |
Aptix is a registered trademark of Aptix Corporation. System Explorer, Explorer, Aptix Prototype Studio, Design Pilot, and Software Integration Station are trademarks of Aptix Corporation. All other registered trademarks or trademarks are property of their respective owners.