Latest deliverables from the long-standing collaboration between Mentor Graphics and ARM provides leading-edge verification solutions for ARM11 core-based designs
WILSONVILLE, Ore., July 15, 2003 - Mentor Graphics Corp. (Nasdaq: MENT) today announced the availability of the Seamless co-verification Processor Support Packages (PSPs) for the ARM1136J-STM and ARM1136JF-STM high-performance cores. These are the first new models delivered under the recently extended licensing and distribution agreement between ARM and Mentor Graphics.
Seamless Hardware/Software Co-Verification for ARM11 Cores
The Seamless® PSPs for the ARM11TM cores are high-performance bus cycle-accurate models which completely simulate pipelines, caches, and the full ARM and Thumb® instruction-sets, including Java extensions. Along with the Seamless PSPs for the ARM7TM, ARM9TM and ARM10TM families, the ARM11 core-based PSPs are amongst the first to implement the Seamless Version 5 Performance Profile Viewer. Users of the ARM11 core-based PSPs can profile software, chart memory transactions, monitor cache efficiency and plot bus utilization and arbitration delay. This data can guide the designer to improvements that can be made to the system's performance.
Seamless provides support for all popular logic simulators, including the Model Technology® ModelSim® environment, as well as many software development environments. The ARM11 core-based PSPs are integrated with debuggers from Mentor Graphics and ARM and have been verified against a range of code development tools and real-time operating systems such as the Mentor Graphics® solution, the NucleusTM tool.
ARM11 core-based PSPs are fully compatible with the Seamless C-BridgeTM technology and the Platform ExpressTM tool. The C-Bridge technology enables the effective verification of ARM® designs implemented entirely in C (including System C) or in mixed C/RTL descriptions using the proven Seamless technology. With the Platform Express ARM11 core-based library, designers can quickly assemble and integrate compatible IP and immediately leverage the full power of Seamless.
Seamless and ARM
First introduced in 1996, the Seamless hardware/software co-verification environment has become firmly established as the market leader with support for over 120 CPUs and DSPs.
"Mentor Graphics is the leading supplier of co-verification solutions for ARM cores," said Duncan Bryan, EDA Relations manager, ARM. "ARM recently renewed and extended our agreement with Mentor Graphics, thereby ensuring our partners' continued early access to the best-in-class co-verification models for new ARM processors."
The ARM11 core-based PSP is built using Modelware, a second generation interface expressly developed by Mentor Graphics for integration of cycle-accurate CPU models with Seamless. The combination of Modelware and ARM's Cycle Callable Models ensures that end customers have quick access to efficient and accurate co-verification solutions for ARM cores. ARM and Mentor Graphics first collaborated on the development of co-verification solutions in 1997. Since then, over 80 customers worldwide have licensed co-verification solutions for ARM cores from Mentor Graphics. ARM partners have deployed the Seamless environment as a critical component of their verification process for such diverse applications as wireless communications, digital imaging, automotive and networking.
The ARM1136J-S and ARM1136JF-S core-based PSPs are available for Solaris, HP/UX and Red Hat Linux platforms. Pricing for ARM core-based PSPs starts at $20,000. For more information or to register for free Seamless workshops and functional verification seminars, visit www.mentor.com/seamless.
Linking popular software development and debug tools with logic simulation, the Seamless environment delivers high performance co-verification months before a hardware prototype can be built. The Seamless environment enables software and hardware development to be parallel activities, removing software from the critical path and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as block memory transfers and algorithmic routines.
To this environment, Seamless Version 5 adds the ability to analyze code, bus and memory performance. These capabilities allow not only the validation of hardware/software interactions, but also give measurement on the quality of the system and guidance on where improvements can be made.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.